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Re: [SH] Allow reg+disp address modes for atomics

On Tue, 2015-02-10 at 18:35 +0900, Kaz Kojima wrote:
> Oleg Endo <> wrote:
> > The attached patch fixes the lost mem aliasing info for atomic ops on SH
> > and allows the utilization of reg+disp address modes for atomic ops.
> > Actually it was supposed to be a pretty straight forward patch that just
> > replaces the open coded 'mem:QIHISI (match_operand:SI
> > "arith_reg_operand")' operands with something like 'match_operand:QIHISI
> > "atomic_mem_operand".  For most of the patterns that's what it does and
> > the changes are quite mechanical.  However, the QIHImode LLCS patterns
> > modify the address register of the mem operand and thus required some
> > special care (additional insns / splits).
> > 
> > I've briefly tested it with
> > make -k check-gcc RUNTESTFLAGS="sh.exp --target_board=sh-sim
> > \{-m2/-ml,-m2/-mb,-m2a/-mb,-m2e/-ml,-m2e/-mb,-m3/-ml,-m3/-mb,-m3e/-ml,-m3e/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}"
> > 
> > to verify that the patterns work in isolation.  However, one thing I'm
> > not sure about is the fact that the predicate 'atomic_mem_operand_*' and
> > the Sra,Sdd,Ara,Add mem constraints are not in sync, i.e. the
> > constraints allow certain things which the predicates do not allow and
> > vice versa.
> > 
> > Kaz, could you please try the patch on sh4-linux?
> No new failures on sh4-unknown-linux-gnu.

Thanks.  Committed as r220594.


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