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RE: [PATCH,WWWDOCS] MIPS changes for GCC 5.0



> -----Original Message-----
> From: Matthew Fortune [mailto:Matthew.Fortune@imgtec.com]
> Sent: Thursday, February 05, 2015 5:24 AM
> To: Moore, Catherine
> Cc: 'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org)
> Subject: RE: [PATCH,WWWDOCS] MIPS changes for GCC 5.0
> 
> Moore, Catherine <Catherine_Moore@mentor.com> writes:
> > Hi Matthew,
> >
> > I made a few edits.  I removed the markup in the process, so that will
> > need to be added back.
> > See the text at the end.
> 
> Thanks Catherine. Good call to remove the markup while reviewing. I've
> done one more pass on this to have the same phrasing used where similar
> points are being made. I also added a comment about link compatibility for
> FP64.  Updated text is at the end.
> 
This looks good now.

> >
> > > -----Original Message-----
> > > From: Matthew Fortune [mailto:Matthew.Fortune@imgtec.com]
> > > Sent: Wednesday, February 04, 2015 11:46 AM
> > > To: Moore, Catherine
> > > Cc: 'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org)
> > > Subject: [PATCH,WWWDOCS] MIPS changes for GCC 5.0
> > >
> > > Hi Catherine,
> > >
> > > I've made a first pass at writing up the MIPS changes for GCC 5.0.
> > > Could you take a read and see what needs some more work?
> > >
> > > Thanks,
> > > Matthew
> > >
> > > Index: htdocs/gcc-5/changes.html
> > >
> ==========================================================
> > > =========
> > > RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-5/changes.html,v
> > > retrieving revision 1.77
> > > diff -r1.77 changes.html
> > > 562a563,614
> > > > <h3 id="mips">MIPS</h3>
> > > >   <ul>
> > > >     <li>MIPS Releases 3 and 5 are now directly supported using
> > > > <code>-
> > > mips32r3,
> > > >     -mips64r3, -mips32r5 and -mips64r5</code> instead of relying
> > > > on the
> > > Release
> > > >     2 options.</li>
> > > >     <li>Support for the Imagination P5600 processor has been added
> > using
> > > >     <code>-march=p5600</code>.
> > > >     </li>
> > > >     <li>Support for the Cavium Networks Octeon3 processor has been
> > > > added
> > > using
> > > >     <code>-march=octeon3</code>.</li>
> > > >     <li>MIPS Release 6 is now supported using <code>-mips32r6 and
> > > > -
> > > mips64r6
> > > >     </code>.
> > > >     <li>The previous o32 64-bit floating-point register support
> > > > has
> > been
> > > >     obsoleted and removed.  This was previously enabled using
> > > > <code>-
> > > mfp64
> > > >     </code> which has been re-purposed for the new ABI extensions
> > > described
> > > >     below.</li>
> > > >     <li>New o32 ABI extensions have been added to enable software
> > > > to
> > > transition
> > > >     away from the original layout of double-precision
> > > > floating-point
> > registers.
> > > >     <ul>
> > > >       <li>The first of these extensions is o32 FPXX which places
> > restrictions
> > > >       on code-generation to never access the upper 32-bits of
> > > > double-
> > > precision
> > > >       registers via odd-numbered single-precision registers.  By
> > default the
> > > >       odd-numbered single-precision registers are not used at all
> > with this
> > > >       extension.  o32 FPXX code is link compatible with all other
> > o32
> > > >       double-precision ABI variants and will execute correctly in
> > all hardware
> > > >       FPU modes.  Enable o32 FPXX using <code>-mabi=32
> > > > -mfpxx</code>
> > for
> > > >       MIPS II onwards.</li>
> > > >       <li>The second extension is o32 FP64A which requires 64-bit
> > > >       floating-point registers and places a mandatory restriction
> > > > on
> > the use of
> > > >       odd-numbered single-precision registers.  o32 FP64A is link
> > compatible
> > > >       with all other o32 double-precision ABI variants.  Enable
> > > > o32
> > FP64A
> > > >       using <code>-mabi=32 -mfp64 -mno-odd-spreg</code> for
> > > > MIPS32R2
> > > onwards.
> > > >       </li>
> > > >       <li>Finally, the o32 FP64 extension which also requires 64-bit
> > > >       floating-point registers but permits the use of all single-
> > precision
> > > >       registers.  Enable o32 FP64 using <code>-mfp64</code> for
> > MIPS32R2
> > > >       onwards.</li>
> > > >     </ul>
> > > >     All new ABI variants can be enabled by default using configure
> > time
> > > >     options <code>--with-fp-32=[32|xx|64]</code> and
> > > >     <code>--with(out)-odd-sp-reg-32</code>.  It is strongly
> > > > recommended
> > > that
> > > >     all vendors begin to set o32 FPXX as default ABI to be able to
> > run the
> > > >     generated code on MIPSR5 cores alongside future MIPS SIMD
> > > > (MSA)
> > > code and
> > > >     MIPSR6 cores.</li>
> > > >     <li>When using binutils 2.25 GCC will now pass options like
> > > >     <code>-msoft-float</code> and <code>-msingle-float</code> to
> > > > the
> > > assembler.
> > > >     This change can affect inline assembly code that is built as
> > soft-float but
> > > >     contains hard-float instructions.  In such cases the code must
> > > > be
> > > amended
> > > >     to use appropriate <code>.set</code> directives to override
> > > > the
> > global
> > > >     assembler options.</li>
> > > >   </ul>
> > > >
> >
> > MIPS Releases 3 and 5 are now directly supported.  Use the
> > command-line options -mips32r3, -mips64r3, -mips32r5 and -mips64r5 to
> > enable code- generation for these processors.
> >
> > Support for the Imagination P5600 processor is now supported through
> > use of the -march=p5600 command-line option.
> >
> > The Cavium Octeon3 processor is now supported through the use of the
> > command-line option -march=octeon3.
> >
> > MIPS Release 6 is now supported through the use of the -mips32r6 and -
> > mips64r6 command-line options.
> >
> > The o32 ABI has been modified and extended.  The o32 64-bit floating-
> > point register support is now obsolete and has been removed.  It has
> > been replaced by three ABI extensions FPXX, FP64A, and FP64.  The
> > meaning of the -mfp64 command-line option has been changed and it is
> > now used to enable the ABI extensions.
> >
> > The FPXX extension requires that code generated to access double-
> > precision values use even-numbered registers.  Code that adheres to
> > this extension is link-compatible with the other o32 double-precision
> > ABI variants and will execute correctly in all hardware FPU modes.
> > The command-line options
> > -mabi=32 -mfpxx can be used to enable this extension.  MIPS II is the
> > minimum processor required.
> >
> > The o32 FP64A extension requires that floating-point registers be 64-
> > bits and odd-numbered single-precisions registers are not allowed.
> > Code that adheres to the The o32 FP64A variant is link-compatible with
> > the other
> > o32 double-precision ABI variants.  The command-line options -mabi=32
> > -mfp64 -mno-odd-spreg can be used to enable this extension.  MIPS32R2
> > is the minimum processor required.
> >
> > The o32 FP64 extension also requires that floating-point registers be
> > 64-bits, but permits the use of single-precision registers.  The o32
> > FP64 extension is enabled by using the -mfp64 command-line option.
> > MIPS32R2 is the minimum processor required.
> >
> > The new ABI variants can be enabled by default using the configure
> > time options --with-fp-32=[32|xx|64] and --with(out)-odd-sp-reg-32.
> > It is strongly recommended that all vendors begin to set o32 FPXX as
> > the default ABI.  This will be required to run the generated code on
> > MIPSR5 cores in conjunction with future MIPS SIMD (MSA) code and
> MIPSR6 cores.
> >
> > GCC will now pass explicit floating-point options to the assembler if
> > GNU binutils 2.25 is being used.  As a result, any inline assembly
> > code that uses hard-float instructions should be amended to include a
> > .set directive to override the global assembler options when compiling
> > for soft-float targets.
> 
> MIPS Releases 3 and 5 are now directly supported.  Use the command-line
> options -mips32r3, -mips64r3, -mips32r5 and -mips64r5 to enable code-
> generation for these processors.
> 
> The Imagination P5600 processor is now supported using the -march=p5600
> command-line option.
> 
> The Cavium Octeon3 processor is now supported using the command-line
> option -march=octeon3.
> 
> MIPS Release 6 is now supported using -mips32r6 and -mips64r6 command-
> line options.
> 
> The o32 ABI has been modified and extended.  The o32 64-bit floating- point
> register support is now obsolete and has been removed.  It has been
> replaced by three ABI extensions FPXX, FP64A, and FP64.  The meaning of
> the -mfp64 command-line option has been changed and it is now used to
> enable the FP64A and FP64 ABI extensions.
> 
> The FPXX extension requires that code generated to access double- precision
> values use even-numbered registers.  Code that adheres to this extension is
> link-compatible with all other o32 double-precision ABI variants and will
> execute correctly in all hardware FPU modes.  The command-line options -
> mabi=32 -mfpxx can be used to enable this extension.
> MIPS II is the minimum processor required.
> 
> The o32 FP64A extension requires that floating-point registers be 64-bits and
> odd-numbered single-precision registers are not allowed.  Code that adheres
> to the o32 FP64A variant is link-compatible with all other o32 double-
> precision ABI variants.  The command-line options -mabi=32
> -mfp64 -mno-odd-spreg can be used to enable this extension.  MIPS32R2 is
> the minimum processor required.
> 
> The o32 FP64 extension also requires that floating-point registers be 64-bits,
> but permits the use of single-precision registers.  Code that adheres to the
> o32 FP64 variant is link-compatible with o32 FPXX and
> o32 FP64A variants only, i.e. it is not compatible with the original o32 double-
> precision ABI. The command-line options -mabi=32 -mfp64 -modd-spreg can
> be used to enable this extension.  MIPS32R2 is the minimum processor
> required.
> 
> The new ABI variants can be enabled by default using the configure time
> options --with-fp-32=[32|xx|64] and --with(out)-odd-sp-reg-32.  It is strongly
> recommended that all vendors begin to set o32 FPXX as the default ABI.  This
> will be required to run the generated code on MIPSR5 cores in conjunction
> with future MIPS SIMD (MSA) code and MIPSR6 cores.
> 
> GCC will now pass all floating-point options to the assembler if GNU binutils
> 2.25 is being used.  As a result, any inline assembly code that uses hard-float
> instructions should be amended to include a .set directive to override the
> global assembler options when compiling for soft-float targets.


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