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[ARM] Wire up the new scheduler description for the ARM Cortex-A57 processor
- From: James Greenhalgh <james dot greenhalgh at arm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: richard dot earnshaw at arm dot com, ramana dot radhakrishnan at arm dot com
- Date: Mon, 19 Jan 2015 17:44:27 +0000
- Subject: [ARM] Wire up the new scheduler description for the ARM Cortex-A57 processor
- Authentication-results: sourceware.org; auth=none
- References: <54B8F2A2 dot 2080206 at arm dot com>
On Fri, Jan 16, 2015 at 11:14:42AM +0000, Ramana Radhakrishnan wrote:
>
>
> On 16/01/15 10:20, Marcus Shawcroft wrote:
> > On 15 January 2015 at 09:50, James Greenhalgh <james.greenhalgh@arm.com> wrote:
> >
> >> 2015-01-15 James Greenhalgh <james.greenhalgh@arm.com>
> >>
> >> * config/arm/cortex-a57.md: New.
> >> * config/aarch64/aarch64.md: Include it.
> >> * config/aarch64/aarch64-cores.def (cortex-a57): Tune for it.
> >> * config/aarch64/aarch64-tune.md: Regenerate.
> >
> > This is low risk and only affects aarch64 backend. I think we should
> > take this for gcc 5, so OK.
> >
> > Ramana do you want this wired up for aarch32 in a followup?
>
> Yes please. I think as long as it works, let's just take it for 5.0. I'd
> rather not have divergence between the backends as this just creates
> problems for us elsewhere.
Hi,
OK, that patch looks like this. I know I've missed the stage 3 deadline,
but I agree that the two back ends should not diverge too much - and
this patch is small and gives a nice little boost to performance on
some popular benchmarks.
I've regression tested it over the weekend with no issues.
OK?
Cheers,
James
---
2014-01-19 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/arm-cores.def (cortex-a57): Use the new Cortex-A57
pipeline model.
config/arm/arm.md: Include the new Cortex-A57 model.
(generic_sched): Don't use generic_sched when tuning for
Cortex-A57.
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index fa13eb9..f24fefd 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -166,7 +166,7 @@ ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, 7A, FL_LDSCHED |
/* V8 Architecture Processors */
ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, FL_LDSCHED | FL_CRC32, cortex_a53)
-ARM_CORE("cortex-a57", cortexa57, cortexa15, 8A, FL_LDSCHED | FL_CRC32, cortex_a57)
+ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, FL_LDSCHED | FL_CRC32, cortex_a57)
ARM_CORE("xgene1", xgene1, xgene1, 8A, FL_LDSCHED, xgene1)
/* V8 big.LITTLE implementations */
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 5e6649a5dd39c58fac66bb26e0ffae32d2b4a6b8..149f5bc90d4087c6b1425f8e1fb70503cec18970 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -391,8 +391,8 @@ (define_attr "generic_sched" "yes,no"
arm926ejs,arm1020e,arm1026ejs,arm1136js,\
arm1136jfs,cortexa5,cortexa7,cortexa8,\
cortexa9,cortexa12,cortexa15,cortexa17,\
- cortexa53,cortexm4,cortexm7,marvell_pj4,\
- xgene1")
+ cortexa53,cortexa57,cortexm4,cortexm7,\
+ marvell_pj4,xgene1")
(eq_attr "tune_cortexr4" "yes"))
(const_string "no")
(const_string "yes"))))
@@ -425,6 +425,7 @@ (define_attr "generic_vfp" "yes,no"
(include "cortex-a15.md")
(include "cortex-a17.md")
(include "cortex-a53.md")
+(include "cortex-a57.md")
(include "cortex-r4.md")
(include "cortex-r4f.md")
(include "cortex-m7.md")