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Re: [PATCH, i386] Add prefixes avoidance tuning for silvermont target
- From: Uros Bizjak <ubizjak at gmail dot com>
- To: Ilya Enkovich <enkovich dot gnu at gmail dot com>
- Cc: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>, Jakub Jelinek <jakub at redhat dot com>, Vladimir Makarov <vmakarov at redhat dot com>
- Date: Tue, 2 Dec 2014 12:21:02 +0100
- Subject: Re: [PATCH, i386] Add prefixes avoidance tuning for silvermont target
- Authentication-results: sourceware.org; auth=none
- References: <CAMbmDYYKv+CYsaYH+_gABQomB3o5rfZ+dbO=iiUbKmxjqmKiDg at mail dot gmail dot com> <CAFULd4aL+MYcYH4+bgkCi7=0U9c6GOyzyP8=25X_PcZa4dHWWw at mail dot gmail dot com> <CAMbmDYb167cYiOx5qVuOy=2hxBV6oU_TJWkKzusqTuugyBpHUw at mail dot gmail dot com> <CAFULd4ZtADqy=_jgX5iaAmqpnc+kd3ZaK_8M0kRnGzywHxQ8nA at mail dot gmail dot com> <CAMbmDYaYSBaXNJzeihPzpccfPPR6_g584MfAugYiohwdWwGhxA at mail dot gmail dot com> <CAFULd4aJk1DNZ7tLMKXBPjYYGPsuqGpciK0rqmd3=9cb5ezhqQ at mail dot gmail dot com> <20140715110155 dot GA48158 at msticlxl57 dot ims dot intel dot com> <CAFULd4YhTr6RSVyrg6N98_vR3cPi9D8i0shnsCLRbiiYH-CyUA at mail dot gmail dot com> <CAMbmDYaf1gxGZZ2skruSLCkynXLxC-8SfrJ+gkWU8R7WD6Ni_A at mail dot gmail dot com> <CAFULd4b++WRFHO=UsT8mnaYE9NO9bvfjcjNoZPvFRdzjMJLmNA at mail dot gmail dot com> <20141202110833 dot GB2963 at msticlxl57 dot ims dot intel dot com>
On Tue, Dec 2, 2014 at 12:08 PM, Ilya Enkovich <enkovich.gnu@gmail.com> wrote:
>> > Having stage1 close to end, may we make some decision regarding this
>> > patch? Having a couple of working variants, may we choose and use one
>> > of them?
>>
>> I propose to wait for Vlad for an update about his plans on register
>> preference algorythm that would fix this (and other "Ya*r"-type
>> issues).
>>
>> In the absence of the fix, we'll go with "Yr,*x".
>>
>> Uros.
>>
>
> Hi,
>
> Here is an updated patch which uses "Yr,*x" option to avoid long prefixes for Silvermont. Bootstrapped and tested on x86_64-unknown-linux-gnu. OK for trunk?
>
> Thanks,
> Ilya
> --
> gcc/
>
> 2014-12-02 Ilya Enkovich <ilya.enkovich@intel.com>
>
> * config/i386/constraints.md (Yr): New.
> * config/i386/i386.h (reg_class): Add NO_REX_SSE_REGS.
> (REG_CLASS_NAMES): Likewise.
> (REG_CLASS_CONTENTS): Likewise.
> * config/i386/sse.md (*vec_concatv2sf_sse4_1): Add alternatives
> which use only NO_REX_SSE_REGS.
> (vec_set<mode>_0): Likewise.
> (*vec_setv4sf_sse4_1): Likewise.
> (sse4_1_insertps): Likewise.
> (*sse4_1_extractps): Likewise.
> (*sse4_1_mulv2siv2di3<mask_name>): Likewise.
> (*<sse4_1_avx2>_mul<mode>3<mask_name>): Likewise.
> (*sse4_1_<code><mode>3<mask_name>): Likewise.
> (*sse4_1_<code><mode>3): Likewise.
> (*sse4_1_eqv2di3): Likewise.
> (sse4_2_gtv2di3): Likewise.
> (*vec_extractv4si): Likewise.
> (*vec_concatv2si_sse4_1): Likewise.
> (vec_concatv2di): Likewise.
> (<sse4_1>_blend<ssemodesuffix><avxsizesuffix>): Likewise.
> (<sse4_1>_blendv<ssemodesuffix><avxsizesuffix>): Likewise.
> (<sse4_1>_dp<ssemodesuffix><avxsizesuffix>): Likewise.
> (<vi8_sse4_1_avx2_avx512>_movntdqa): Likewise.
> (<sse4_1_avx2>_mpsadbw): Likewise.
> (<sse4_1_avx2>packusdw<mask_name>): Likewise.
> (<sse4_1_avx2>_pblendvb): Likewise.
> (sse4_1_pblendw): Likewise.
> (sse4_1_phminposuw): Likewise.
> (sse4_1_<code>v8qiv8hi2<mask_name>): Likewise.
> (sse4_1_<code>v4qiv4si2<mask_name>): Likewise.
> (sse4_1_<code>v4hiv4si2<mask_name>): Likewise.
> (sse4_1_<code>v2qiv2di2<mask_name>): Likewise.
> (sse4_1_<code>v2hiv2di2<mask_name>): Likewise.
> (sse4_1_<code>v2siv2di2<mask_name>): Likewise.
> (sse4_1_ptest): Likewise.
> (<sse4_1>_round<ssemodesuffix><avxsizesuffix>): Likewise.
> (sse4_1_round<ssescalarmodesuffix>): Likewise.
> * config/i386/subst.md (mask_prefix4): New.
> * config/i386/x86-tune.def (X86_TUNE_AVOID_4BYTE_PREFIXES): New.
>
> gcc/testsuites/
>
> 2014-12-02 Ilya Enkovich <ilya.enkovich@intel.com>
>
> * gcc.target/i386/sse2-init-v2di-2.c: Adjust to changed
> vec_concatv2di template.
OK for mainline with a change below.
@@ -6544,13 +6550,14 @@
})
(define_insn_and_split "*sse4_1_extractps"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=rm,x,x")
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=*rm,rm,x,x")
(vec_select:SF
Please do not change preferences of non-SSE registers. Please check
the patch that similar changes didn't creep in.
Thanks,
Uros.