[Patch ARM Refactor Builtins 4/8] Refactor "VAR<n>" Macros

[James Greenhalgh <james dot greenhalgh at arm dot com>]

Hi,

These macros can always be defined as a base case of VAR1 and a "recursive"
case of VAR<n-1>. At the moment, the body of VAR1 is duplicated to each
macro.

This patch makes that change.

Regression tested on arm-none-linux-gnueabihf with no issues.

OK?

Thanks,
James

---
gcc/

2014-11-12  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/arm-builtins.c (VAR1): Add a comma.
	(VAR2): Rewrite in terms of VAR1.
	(VAR3-10): Likewise.
	(arm_builtins): Remove leading comma before ARM_BUILTIN_MAX.
	* config/arm/arm_neon_builtins.def: Remove trailing commas.

diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index e387b60..ef86a31 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -134,34 +134,34 @@ typedef struct {
 #define CF(N,X) CODE_FOR_neon_##N##X
 
 #define VAR1(T, N, A) \
-  {#N, NEON_##T, UP (A), CF (N, A), 0}
+  {#N, NEON_##T, UP (A), CF (N, A), 0},
 #define VAR2(T, N, A, B) \
-  VAR1 (T, N, A), \
-  {#N, NEON_##T, UP (B), CF (N, B), 0}
+  VAR1 (T, N, A) \
+  VAR1 (T, N, B)
 #define VAR3(T, N, A, B, C) \
-  VAR2 (T, N, A, B), \
-  {#N, NEON_##T, UP (C), CF (N, C), 0}
+  VAR2 (T, N, A, B) \
+  VAR1 (T, N, C)
 #define VAR4(T, N, A, B, C, D) \
-  VAR3 (T, N, A, B, C), \
-  {#N, NEON_##T, UP (D), CF (N, D), 0}
+  VAR3 (T, N, A, B, C) \
+  VAR1 (T, N, D)
 #define VAR5(T, N, A, B, C, D, E) \
-  VAR4 (T, N, A, B, C, D), \
-  {#N, NEON_##T, UP (E), CF (N, E), 0}
+  VAR4 (T, N, A, B, C, D) \
+  VAR1 (T, N, E)
 #define VAR6(T, N, A, B, C, D, E, F) \
-  VAR5 (T, N, A, B, C, D, E), \
-  {#N, NEON_##T, UP (F), CF (N, F), 0}
+  VAR5 (T, N, A, B, C, D, E) \
+  VAR1 (T, N, F)
 #define VAR7(T, N, A, B, C, D, E, F, G) \
-  VAR6 (T, N, A, B, C, D, E, F), \
-  {#N, NEON_##T, UP (G), CF (N, G), 0}
+  VAR6 (T, N, A, B, C, D, E, F) \
+  VAR1 (T, N, G)
 #define VAR8(T, N, A, B, C, D, E, F, G, H) \
-  VAR7 (T, N, A, B, C, D, E, F, G), \
-  {#N, NEON_##T, UP (H), CF (N, H), 0}
+  VAR7 (T, N, A, B, C, D, E, F, G) \
+  VAR1 (T, N, H)
 #define VAR9(T, N, A, B, C, D, E, F, G, H, I) \
-  VAR8 (T, N, A, B, C, D, E, F, G, H), \
-  {#N, NEON_##T, UP (I), CF (N, I), 0}
+  VAR8 (T, N, A, B, C, D, E, F, G, H) \
+  VAR1 (T, N, I)
 #define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \
-  VAR9 (T, N, A, B, C, D, E, F, G, H, I), \
-  {#N, NEON_##T, UP (J), CF (N, J), 0}
+  VAR9 (T, N, A, B, C, D, E, F, G, H, I) \
+  VAR1 (T, N, J)
 
 /* The NEON builtin data can be found in arm_neon_builtins.def.
    The mode entries in the following table correspond to the "key" type of the
@@ -179,46 +179,10 @@ static neon_builtin_datum neon_builtin_data[] =
 
 #undef CF
 #undef VAR1
-#undef VAR2
-#undef VAR3
-#undef VAR4
-#undef VAR5
-#undef VAR6
-#undef VAR7
-#undef VAR8
-#undef VAR9
-#undef VAR10
 
-#define CF(N,X) ARM_BUILTIN_NEON_##N##X
-#define VAR1(T, N, A) \
-  CF (N, A)
-#define VAR2(T, N, A, B) \
-  VAR1 (T, N, A), \
-  CF (N, B)
-#define VAR3(T, N, A, B, C) \
-  VAR2 (T, N, A, B), \
-  CF (N, C)
-#define VAR4(T, N, A, B, C, D) \
-  VAR3 (T, N, A, B, C), \
-  CF (N, D)
-#define VAR5(T, N, A, B, C, D, E) \
-  VAR4 (T, N, A, B, C, D), \
-  CF (N, E)
-#define VAR6(T, N, A, B, C, D, E, F) \
-  VAR5 (T, N, A, B, C, D, E), \
-  CF (N, F)
-#define VAR7(T, N, A, B, C, D, E, F, G) \
-  VAR6 (T, N, A, B, C, D, E, F), \
-  CF (N, G)
-#define VAR8(T, N, A, B, C, D, E, F, G, H) \
-  VAR7 (T, N, A, B, C, D, E, F, G), \
-  CF (N, H)
-#define VAR9(T, N, A, B, C, D, E, F, G, H, I) \
-  VAR8 (T, N, A, B, C, D, E, F, G, H), \
-  CF (N, I)
-#define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \
-  VAR9 (T, N, A, B, C, D, E, F, G, H, I), \
-  CF (N, J)
+#define VAR1(T, N, X) \
+  ARM_BUILTIN_NEON_##N##X,
+
 enum arm_builtins
 {
   ARM_BUILTIN_GETWCGR0,
@@ -496,7 +460,7 @@ enum arm_builtins
 
 #include "arm_neon_builtins.def"
 
-  ,ARM_BUILTIN_MAX
+  ARM_BUILTIN_MAX
 };
 
 #define ARM_BUILTIN_NEON_BASE (ARM_BUILTIN_MAX - ARRAY_SIZE (neon_builtin_data))
diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
index 5451524..88f0788 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -18,264 +18,264 @@
    along with GCC; see the file COPYING3.  If not see
    <http://www.gnu.org/licenses/>.  */
 
-VAR2 (BINOP, vadd, v2sf, v4sf),
-VAR3 (BINOP, vaddls, v8qi, v4hi, v2si),
-VAR3 (BINOP, vaddlu, v8qi, v4hi, v2si),
-VAR3 (BINOP, vaddws, v8qi, v4hi, v2si),
-VAR3 (BINOP, vaddwu, v8qi, v4hi, v2si),
-VAR6 (BINOP, vhaddu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR6 (BINOP, vhadds, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR6 (BINOP, vrhaddu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR6 (BINOP, vrhadds, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR8 (BINOP, vqadds, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR8 (BINOP, vqaddu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR3 (BINOP, vaddhn, v8hi, v4si, v2di),
-VAR3 (BINOP, vraddhn, v8hi, v4si, v2di),
-VAR2 (BINOP, vmulf, v2sf, v4sf),
-VAR2 (BINOP, vmulp, v8qi, v16qi),
-VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
-VAR3 (TERNOP, vmlals, v8qi, v4hi, v2si),
-VAR3 (TERNOP, vmlalu, v8qi, v4hi, v2si),
-VAR2 (TERNOP, vfma, v2sf, v4sf),
-VAR2 (TERNOP, vfms, v2sf, v4sf),
-VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
-VAR3 (TERNOP, vmlsls, v8qi, v4hi, v2si),
-VAR3 (TERNOP, vmlslu, v8qi, v4hi, v2si),
-VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si),
-VAR4 (BINOP, vqrdmulh, v4hi, v2si, v8hi, v4si),
-VAR2 (TERNOP, vqdmlal, v4hi, v2si),
-VAR2 (TERNOP, vqdmlsl, v4hi, v2si),
-VAR3 (BINOP, vmullp, v8qi, v4hi, v2si),
-VAR3 (BINOP, vmulls, v8qi, v4hi, v2si),
-VAR3 (BINOP, vmullu, v8qi, v4hi, v2si),
-VAR2 (SCALARMULL, vmulls_n, v4hi, v2si),
-VAR2 (SCALARMULL, vmullu_n, v4hi, v2si),
-VAR2 (LANEMULL, vmulls_lane, v4hi, v2si),
-VAR2 (LANEMULL, vmullu_lane, v4hi, v2si),
-VAR2 (SCALARMULL, vqdmull_n, v4hi, v2si),
-VAR2 (LANEMULL, vqdmull_lane, v4hi, v2si),
-VAR4 (SCALARMULH, vqdmulh_n, v4hi, v2si, v8hi, v4si),
-VAR4 (SCALARMULH, vqrdmulh_n, v4hi, v2si, v8hi, v4si),
-VAR4 (LANEMULH, vqdmulh_lane, v4hi, v2si, v8hi, v4si),
-VAR4 (LANEMULH, vqrdmulh_lane, v4hi, v2si, v8hi, v4si),
-VAR2 (BINOP, vqdmull, v4hi, v2si),
-VAR8 (BINOP, vshls, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR8 (BINOP, vshlu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR8 (BINOP, vrshls, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR8 (BINOP, vrshlu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR8 (BINOP, vqshls, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR8 (BINOP, vqshlu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR8 (BINOP, vqrshls, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR8 (BINOP, vqrshlu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR8 (SHIFTIMM, vshrs_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR8 (SHIFTIMM, vshru_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR8 (SHIFTIMM, vrshrs_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR8 (SHIFTIMM, vrshru_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR3 (SHIFTIMM, vshrn_n, v8hi, v4si, v2di),
-VAR3 (SHIFTIMM, vrshrn_n, v8hi, v4si, v2di),
-VAR3 (SHIFTIMM, vqshrns_n, v8hi, v4si, v2di),
-VAR3 (SHIFTIMM, vqshrnu_n, v8hi, v4si, v2di),
-VAR3 (SHIFTIMM, vqrshrns_n, v8hi, v4si, v2di),
-VAR3 (SHIFTIMM, vqrshrnu_n, v8hi, v4si, v2di),
-VAR3 (SHIFTIMM, vqshrun_n, v8hi, v4si, v2di),
-VAR3 (SHIFTIMM, vqrshrun_n, v8hi, v4si, v2di),
-VAR8 (SHIFTIMM, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR8 (SHIFTIMM, vqshl_s_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR8 (SHIFTIMM, vqshl_u_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR3 (SHIFTIMM, vshlls_n, v8qi, v4hi, v2si),
-VAR3 (SHIFTIMM, vshllu_n, v8qi, v4hi, v2si),
-VAR8 (SHIFTACC, vsras_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR8 (SHIFTACC, vsrau_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR8 (SHIFTACC, vrsras_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR8 (SHIFTACC, vrsrau_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR2 (BINOP, vsub, v2sf, v4sf),
-VAR3 (BINOP, vsubls, v8qi, v4hi, v2si),
-VAR3 (BINOP, vsublu, v8qi, v4hi, v2si),
-VAR3 (BINOP, vsubws, v8qi, v4hi, v2si),
-VAR3 (BINOP, vsubwu, v8qi, v4hi, v2si),
-VAR8 (BINOP, vqsubs, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR8 (BINOP, vqsubu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR6 (BINOP, vhsubs, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR6 (BINOP, vhsubu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR3 (BINOP, vsubhn, v8hi, v4si, v2di),
-VAR3 (BINOP, vrsubhn, v8hi, v4si, v2di),
-VAR8 (BINOP, vceq, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
-VAR8 (BINOP, vcge, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
-VAR6 (BINOP, vcgeu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
-VAR6 (BINOP, vcgtu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR2 (BINOP, vcage, v2sf, v4sf),
-VAR2 (BINOP, vcagt, v2sf, v4sf),
-VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR6 (BINOP, vabds, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR6 (BINOP, vabdu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR2 (BINOP, vabdf, v2sf, v4sf),
-VAR3 (BINOP, vabdls, v8qi, v4hi, v2si),
-VAR3 (BINOP, vabdlu, v8qi, v4hi, v2si),
+VAR2 (BINOP, vadd, v2sf, v4sf)
+VAR3 (BINOP, vaddls, v8qi, v4hi, v2si)
+VAR3 (BINOP, vaddlu, v8qi, v4hi, v2si)
+VAR3 (BINOP, vaddws, v8qi, v4hi, v2si)
+VAR3 (BINOP, vaddwu, v8qi, v4hi, v2si)
+VAR6 (BINOP, vhaddu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR6 (BINOP, vhadds, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR6 (BINOP, vrhaddu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR6 (BINOP, vrhadds, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR8 (BINOP, vqadds, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR8 (BINOP, vqaddu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR3 (BINOP, vaddhn, v8hi, v4si, v2di)
+VAR3 (BINOP, vraddhn, v8hi, v4si, v2di)
+VAR2 (BINOP, vmulf, v2sf, v4sf)
+VAR2 (BINOP, vmulp, v8qi, v16qi)
+VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
+VAR3 (TERNOP, vmlals, v8qi, v4hi, v2si)
+VAR3 (TERNOP, vmlalu, v8qi, v4hi, v2si)
+VAR2 (TERNOP, vfma, v2sf, v4sf)
+VAR2 (TERNOP, vfms, v2sf, v4sf)
+VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
+VAR3 (TERNOP, vmlsls, v8qi, v4hi, v2si)
+VAR3 (TERNOP, vmlslu, v8qi, v4hi, v2si)
+VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si)
+VAR4 (BINOP, vqrdmulh, v4hi, v2si, v8hi, v4si)
+VAR2 (TERNOP, vqdmlal, v4hi, v2si)
+VAR2 (TERNOP, vqdmlsl, v4hi, v2si)
+VAR3 (BINOP, vmullp, v8qi, v4hi, v2si)
+VAR3 (BINOP, vmulls, v8qi, v4hi, v2si)
+VAR3 (BINOP, vmullu, v8qi, v4hi, v2si)
+VAR2 (SCALARMULL, vmulls_n, v4hi, v2si)
+VAR2 (SCALARMULL, vmullu_n, v4hi, v2si)
+VAR2 (LANEMULL, vmulls_lane, v4hi, v2si)
+VAR2 (LANEMULL, vmullu_lane, v4hi, v2si)
+VAR2 (SCALARMULL, vqdmull_n, v4hi, v2si)
+VAR2 (LANEMULL, vqdmull_lane, v4hi, v2si)
+VAR4 (SCALARMULH, vqdmulh_n, v4hi, v2si, v8hi, v4si)
+VAR4 (SCALARMULH, vqrdmulh_n, v4hi, v2si, v8hi, v4si)
+VAR4 (LANEMULH, vqdmulh_lane, v4hi, v2si, v8hi, v4si)
+VAR4 (LANEMULH, vqrdmulh_lane, v4hi, v2si, v8hi, v4si)
+VAR2 (BINOP, vqdmull, v4hi, v2si)
+VAR8 (BINOP, vshls, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR8 (BINOP, vshlu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR8 (BINOP, vrshls, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR8 (BINOP, vrshlu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR8 (BINOP, vqshls, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR8 (BINOP, vqshlu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR8 (BINOP, vqrshls, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR8 (BINOP, vqrshlu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR8 (SHIFTIMM, vshrs_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR8 (SHIFTIMM, vshru_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR8 (SHIFTIMM, vrshrs_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR8 (SHIFTIMM, vrshru_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR3 (SHIFTIMM, vshrn_n, v8hi, v4si, v2di)
+VAR3 (SHIFTIMM, vrshrn_n, v8hi, v4si, v2di)
+VAR3 (SHIFTIMM, vqshrns_n, v8hi, v4si, v2di)
+VAR3 (SHIFTIMM, vqshrnu_n, v8hi, v4si, v2di)
+VAR3 (SHIFTIMM, vqrshrns_n, v8hi, v4si, v2di)
+VAR3 (SHIFTIMM, vqrshrnu_n, v8hi, v4si, v2di)
+VAR3 (SHIFTIMM, vqshrun_n, v8hi, v4si, v2di)
+VAR3 (SHIFTIMM, vqrshrun_n, v8hi, v4si, v2di)
+VAR8 (SHIFTIMM, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR8 (SHIFTIMM, vqshl_s_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR8 (SHIFTIMM, vqshl_u_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR3 (SHIFTIMM, vshlls_n, v8qi, v4hi, v2si)
+VAR3 (SHIFTIMM, vshllu_n, v8qi, v4hi, v2si)
+VAR8 (SHIFTACC, vsras_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR8 (SHIFTACC, vsrau_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR8 (SHIFTACC, vrsras_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR8 (SHIFTACC, vrsrau_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR2 (BINOP, vsub, v2sf, v4sf)
+VAR3 (BINOP, vsubls, v8qi, v4hi, v2si)
+VAR3 (BINOP, vsublu, v8qi, v4hi, v2si)
+VAR3 (BINOP, vsubws, v8qi, v4hi, v2si)
+VAR3 (BINOP, vsubwu, v8qi, v4hi, v2si)
+VAR8 (BINOP, vqsubs, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR8 (BINOP, vqsubu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR6 (BINOP, vhsubs, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR6 (BINOP, vhsubu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR3 (BINOP, vsubhn, v8hi, v4si, v2di)
+VAR3 (BINOP, vrsubhn, v8hi, v4si, v2di)
+VAR8 (BINOP, vceq, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
+VAR8 (BINOP, vcge, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
+VAR6 (BINOP, vcgeu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
+VAR6 (BINOP, vcgtu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR2 (BINOP, vcage, v2sf, v4sf)
+VAR2 (BINOP, vcagt, v2sf, v4sf)
+VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR6 (BINOP, vabds, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR6 (BINOP, vabdu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR2 (BINOP, vabdf, v2sf, v4sf)
+VAR3 (BINOP, vabdls, v8qi, v4hi, v2si)
+VAR3 (BINOP, vabdlu, v8qi, v4hi, v2si)
 
-VAR6 (TERNOP, vabas, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR6 (TERNOP, vabau, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR3 (TERNOP, vabals, v8qi, v4hi, v2si),
-VAR3 (TERNOP, vabalu, v8qi, v4hi, v2si),
+VAR6 (TERNOP, vabas, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR6 (TERNOP, vabau, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR3 (TERNOP, vabals, v8qi, v4hi, v2si)
+VAR3 (TERNOP, vabalu, v8qi, v4hi, v2si)
 
-VAR6 (BINOP, vmaxs, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR6 (BINOP, vmaxu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR2 (BINOP, vmaxf, v2sf, v4sf),
-VAR6 (BINOP, vmins, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR6 (BINOP, vminu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR2 (BINOP, vminf, v2sf, v4sf),
+VAR6 (BINOP, vmaxs, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR6 (BINOP, vmaxu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR2 (BINOP, vmaxf, v2sf, v4sf)
+VAR6 (BINOP, vmins, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR6 (BINOP, vminu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR2 (BINOP, vminf, v2sf, v4sf)
 
-VAR3 (BINOP, vpmaxs, v8qi, v4hi, v2si),
-VAR3 (BINOP, vpmaxu, v8qi, v4hi, v2si),
-VAR1 (BINOP, vpmaxf, v2sf),
-VAR3 (BINOP, vpmins, v8qi, v4hi, v2si),
-VAR3 (BINOP, vpminu, v8qi, v4hi, v2si),
-VAR1 (BINOP, vpminf, v2sf),
+VAR3 (BINOP, vpmaxs, v8qi, v4hi, v2si)
+VAR3 (BINOP, vpmaxu, v8qi, v4hi, v2si)
+VAR1 (BINOP, vpmaxf, v2sf)
+VAR3 (BINOP, vpmins, v8qi, v4hi, v2si)
+VAR3 (BINOP, vpminu, v8qi, v4hi, v2si)
+VAR1 (BINOP, vpminf, v2sf)
 
-VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf),
-VAR6 (UNOP, vpaddls, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR6 (UNOP, vpaddlu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR6 (BINOP, vpadals, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR6 (BINOP, vpadalu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR2 (BINOP, vrecps, v2sf, v4sf),
-VAR2 (BINOP, vrsqrts, v2sf, v4sf),
-VAR8 (SHIFTINSERT, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR8 (SHIFTINSERT, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
-VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
-VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR6 (UNOP, vcls, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-VAR5 (BSWAP, bswap, v4hi, v8hi, v2si, v4si, v2di),
-VAR2 (UNOP, vcnt, v8qi, v16qi),
-VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf),
-VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf),
-VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
+VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf)
+VAR6 (UNOP, vpaddls, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR6 (UNOP, vpaddlu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR6 (BINOP, vpadals, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR6 (BINOP, vpadalu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR2 (BINOP, vrecps, v2sf, v4sf)
+VAR2 (BINOP, vrsqrts, v2sf, v4sf)
+VAR8 (SHIFTINSERT, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR8 (SHIFTINSERT, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
+VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
+VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR6 (UNOP, vcls, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+VAR5 (BSWAP, bswap, v4hi, v8hi, v2si, v4si, v2di)
+VAR2 (UNOP, vcnt, v8qi, v16qi)
+VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf)
+VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf)
+VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
   /* FIXME: vget_lane supports more variants than this!  */
 VAR10 (GETLANE, vget_lane,
-	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
-VAR6 (GETLANE, vget_laneu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
+	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
+VAR6 (GETLANE, vget_laneu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
 VAR10 (SETLANE, vset_lane,
-	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
-VAR5 (CREATE, vcreate, v8qi, v4hi, v2si, v2sf, di),
+	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
+VAR5 (CREATE, vcreate, v8qi, v4hi, v2si, v2sf, di)
 VAR10 (DUP, vdup_n,
-	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
+	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
 VAR10 (BINOP, vdup_lane,
-	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
-VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di),
-VAR5 (SPLIT, vget_high, v16qi, v8hi, v4si, v4sf, v2di),
-VAR5 (SPLIT, vget_low, v16qi, v8hi, v4si, v4sf, v2di),
-VAR3 (UNOP, vmovn, v8hi, v4si, v2di),
-VAR3 (UNOP, vqmovns, v8hi, v4si, v2di),
-VAR3 (UNOP, vqmovnu, v8hi, v4si, v2di),
-VAR3 (UNOP, vqmovun, v8hi, v4si, v2di),
-VAR3 (UNOP, vmovls, v8qi, v4hi, v2si),
-VAR3 (UNOP, vmovlu, v8qi, v4hi, v2si),
-VAR6 (LANEMUL, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
-VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
-VAR2 (LANEMAC, vmlals_lane, v4hi, v2si),
-VAR2 (LANEMAC, vmlalu_lane, v4hi, v2si),
-VAR2 (LANEMAC, vqdmlal_lane, v4hi, v2si),
-VAR6 (LANEMAC, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
-VAR2 (LANEMAC, vmlsls_lane, v4hi, v2si),
-VAR2 (LANEMAC, vmlslu_lane, v4hi, v2si),
-VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si),
-VAR6 (SCALARMUL, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
-VAR6 (SCALARMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
-VAR2 (SCALARMAC, vmlals_n, v4hi, v2si),
-VAR2 (SCALARMAC, vmlalu_n, v4hi, v2si),
-VAR2 (SCALARMAC, vqdmlal_n, v4hi, v2si),
-VAR6 (SCALARMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
-VAR2 (SCALARMAC, vmlsls_n, v4hi, v2si),
-VAR2 (SCALARMAC, vmlslu_n, v4hi, v2si),
-VAR2 (SCALARMAC, vqdmlsl_n, v4hi, v2si),
+	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
+VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di)
+VAR5 (SPLIT, vget_high, v16qi, v8hi, v4si, v4sf, v2di)
+VAR5 (SPLIT, vget_low, v16qi, v8hi, v4si, v4sf, v2di)
+VAR3 (UNOP, vmovn, v8hi, v4si, v2di)
+VAR3 (UNOP, vqmovns, v8hi, v4si, v2di)
+VAR3 (UNOP, vqmovnu, v8hi, v4si, v2di)
+VAR3 (UNOP, vqmovun, v8hi, v4si, v2di)
+VAR3 (UNOP, vmovls, v8qi, v4hi, v2si)
+VAR3 (UNOP, vmovlu, v8qi, v4hi, v2si)
+VAR6 (LANEMUL, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
+VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
+VAR2 (LANEMAC, vmlals_lane, v4hi, v2si)
+VAR2 (LANEMAC, vmlalu_lane, v4hi, v2si)
+VAR2 (LANEMAC, vqdmlal_lane, v4hi, v2si)
+VAR6 (LANEMAC, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
+VAR2 (LANEMAC, vmlsls_lane, v4hi, v2si)
+VAR2 (LANEMAC, vmlslu_lane, v4hi, v2si)
+VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si)
+VAR6 (SCALARMUL, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
+VAR6 (SCALARMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
+VAR2 (SCALARMAC, vmlals_n, v4hi, v2si)
+VAR2 (SCALARMAC, vmlalu_n, v4hi, v2si)
+VAR2 (SCALARMAC, vqdmlal_n, v4hi, v2si)
+VAR6 (SCALARMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
+VAR2 (SCALARMAC, vmlsls_n, v4hi, v2si)
+VAR2 (SCALARMAC, vmlslu_n, v4hi, v2si)
+VAR2 (SCALARMAC, vqdmlsl_n, v4hi, v2si)
 VAR10 (SHIFTINSERT, vext,
-	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
-VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
-VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi),
-VAR2 (UNOP, vrev16, v8qi, v16qi),
-VAR4 (CONVERT, vcvts, v2si, v2sf, v4si, v4sf),
-VAR4 (CONVERT, vcvtu, v2si, v2sf, v4si, v4sf),
-VAR4 (FIXCONV, vcvts_n, v2si, v2sf, v4si, v4sf),
-VAR4 (FIXCONV, vcvtu_n, v2si, v2sf, v4si, v4sf),
-VAR1 (FLOAT_WIDEN, vcvtv4sf, v4hf),
-VAR1 (FLOAT_NARROW, vcvtv4hf, v4sf),
+	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
+VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
+VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi)
+VAR2 (UNOP, vrev16, v8qi, v16qi)
+VAR4 (CONVERT, vcvts, v2si, v2sf, v4si, v4sf)
+VAR4 (CONVERT, vcvtu, v2si, v2sf, v4si, v4sf)
+VAR4 (FIXCONV, vcvts_n, v2si, v2sf, v4si, v4sf)
+VAR4 (FIXCONV, vcvtu_n, v2si, v2sf, v4si, v4sf)
+VAR1 (FLOAT_WIDEN, vcvtv4sf, v4hf)
+VAR1 (FLOAT_NARROW, vcvtv4hf, v4sf)
 VAR10 (SELECT, vbsl,
-	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
-VAR2 (COPYSIGNF, copysignf, v2sf, v4sf),
-VAR2 (RINT, vrintn, v2sf, v4sf),
-VAR2 (RINT, vrinta, v2sf, v4sf),
-VAR2 (RINT, vrintp, v2sf, v4sf),
-VAR2 (RINT, vrintm, v2sf, v4sf),
-VAR2 (RINT, vrintz, v2sf, v4sf),
-VAR2 (RINT, vrintx, v2sf, v4sf),
-VAR1 (RINT, vcvtav2sf, v2si),
-VAR1 (RINT, vcvtav4sf, v4si),
-VAR1 (RINT, vcvtauv2sf, v2si),
-VAR1 (RINT, vcvtauv4sf, v4si),
-VAR1 (RINT, vcvtpv2sf, v2si),
-VAR1 (RINT, vcvtpv4sf, v4si),
-VAR1 (RINT, vcvtpuv2sf, v2si),
-VAR1 (RINT, vcvtpuv4sf, v4si),
-VAR1 (RINT, vcvtmv2sf, v2si),
-VAR1 (RINT, vcvtmv4sf, v4si),
-VAR1 (RINT, vcvtmuv2sf, v2si),
-VAR1 (RINT, vcvtmuv4sf, v4si),
-VAR1 (VTBL, vtbl1, v8qi),
-VAR1 (VTBL, vtbl2, v8qi),
-VAR1 (VTBL, vtbl3, v8qi),
-VAR1 (VTBL, vtbl4, v8qi),
-VAR1 (VTBX, vtbx1, v8qi),
-VAR1 (VTBX, vtbx2, v8qi),
-VAR1 (VTBX, vtbx3, v8qi),
-VAR1 (VTBX, vtbx4, v8qi),
-VAR5 (REINTERP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di),
-VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di),
-VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di),
-VAR5 (REINTERP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di),
-VAR5 (REINTERP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di),
-VAR6 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di, ti),
-VAR6 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di, ti),
-VAR6 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di, ti),
-VAR6 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di, ti),
-VAR6 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di, ti),
-VAR6 (REINTERP, vreinterpretti, v16qi, v8hi, v4si, v4sf, v2di, ti),
+	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
+VAR2 (COPYSIGNF, copysignf, v2sf, v4sf)
+VAR2 (RINT, vrintn, v2sf, v4sf)
+VAR2 (RINT, vrinta, v2sf, v4sf)
+VAR2 (RINT, vrintp, v2sf, v4sf)
+VAR2 (RINT, vrintm, v2sf, v4sf)
+VAR2 (RINT, vrintz, v2sf, v4sf)
+VAR2 (RINT, vrintx, v2sf, v4sf)
+VAR1 (RINT, vcvtav2sf, v2si)
+VAR1 (RINT, vcvtav4sf, v4si)
+VAR1 (RINT, vcvtauv2sf, v2si)
+VAR1 (RINT, vcvtauv4sf, v4si)
+VAR1 (RINT, vcvtpv2sf, v2si)
+VAR1 (RINT, vcvtpv4sf, v4si)
+VAR1 (RINT, vcvtpuv2sf, v2si)
+VAR1 (RINT, vcvtpuv4sf, v4si)
+VAR1 (RINT, vcvtmv2sf, v2si)
+VAR1 (RINT, vcvtmv4sf, v4si)
+VAR1 (RINT, vcvtmuv2sf, v2si)
+VAR1 (RINT, vcvtmuv4sf, v4si)
+VAR1 (VTBL, vtbl1, v8qi)
+VAR1 (VTBL, vtbl2, v8qi)
+VAR1 (VTBL, vtbl3, v8qi)
+VAR1 (VTBL, vtbl4, v8qi)
+VAR1 (VTBX, vtbx1, v8qi)
+VAR1 (VTBX, vtbx2, v8qi)
+VAR1 (VTBX, vtbx3, v8qi)
+VAR1 (VTBX, vtbx4, v8qi)
+VAR5 (REINTERP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di)
+VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di)
+VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di)
+VAR5 (REINTERP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di)
+VAR5 (REINTERP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di)
+VAR6 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di, ti)
+VAR6 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di, ti)
+VAR6 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di, ti)
+VAR6 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di, ti)
+VAR6 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di, ti)
+VAR6 (REINTERP, vreinterpretti, v16qi, v8hi, v4si, v4sf, v2di, ti)
 VAR10 (LOAD1, vld1,
-         v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
+        v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
 VAR10 (LOAD1LANE, vld1_lane,
-	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
+	v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
 VAR10 (LOAD1, vld1_dup,
-	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
+	v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
 VAR10 (STORE1, vst1,
-	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
+	v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
 VAR10 (STORE1LANE, vst1_lane,
-	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
-VAR9 (LOADSTRUCT,
-	vld2, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
+	v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
+VAR9 (LOADSTRUCT, vld2,
+	v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf)
 VAR7 (LOADSTRUCTLANE, vld2_lane,
-	v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
-VAR5 (LOADSTRUCT, vld2_dup, v8qi, v4hi, v2si, v2sf, di),
+	v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
+VAR5 (LOADSTRUCT, vld2_dup, v8qi, v4hi, v2si, v2sf, di)
 VAR9 (STORESTRUCT, vst2,
-	v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
+	v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf)
 VAR7 (STORESTRUCTLANE, vst2_lane,
-	v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
-VAR9 (LOADSTRUCT,
-	vld3, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
+	v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
+VAR9 (LOADSTRUCT, vld3,
+	v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf)
 VAR7 (LOADSTRUCTLANE, vld3_lane,
-	v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
-VAR5 (LOADSTRUCT, vld3_dup, v8qi, v4hi, v2si, v2sf, di),
+	v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
+VAR5 (LOADSTRUCT, vld3_dup, v8qi, v4hi, v2si, v2sf, di)
 VAR9 (STORESTRUCT, vst3,
-	v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
+	v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf)
 VAR7 (STORESTRUCTLANE, vst3_lane,
-	v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
+	v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
 VAR9 (LOADSTRUCT, vld4,
-	v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
+	v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf)
 VAR7 (LOADSTRUCTLANE, vld4_lane,
-	v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
-VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di),
+	v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
+VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di)
 VAR9 (STORESTRUCT, vst4,
-	v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
+	v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf)
 VAR7 (STORESTRUCTLANE, vst4_lane,
 	v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf)