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RE: [Ping] [PATCH, 7/10] aarch64: add function to output ccmp insn
- From: "Zhenqiang Chen" <zhenqiang dot chen at arm dot com>
- To: "'Richard Henderson'" <rth at redhat dot com>
- Cc: <gcc-patches at gcc dot gnu dot org>
- Date: Mon, 27 Oct 2014 15:49:12 +0800
- Subject: RE: [Ping] [PATCH, 7/10] aarch64: add function to output ccmp insn
- Authentication-results: sourceware.org; auth=none
- References: <001501cfd6f9$f23eb3b0$d6bc1b10$ at arm dot com> <543956B4 dot 7050800 at redhat dot com> <543A08DA dot 6010802 at redhat dot com>
> -----Original Message-----
> From: Richard Henderson [mailto:rth@redhat.com]
> Sent: Sunday, October 12, 2014 12:52 PM
> To: Zhenqiang Chen; gcc-patches@gcc.gnu.org
> Subject: Re: [Ping] [PATCH, 7/10] aarch64: add function to output ccmp
insn
>
> On 10/11/2014 09:11 AM, Richard Henderson wrote:
> > On 09/22/2014 11:45 PM, Zhenqiang Chen wrote:
> >> +static unsigned int
> >> +aarch64_code_to_nzcv (enum rtx_code code, bool inverse) {
> >> + switch (code)
> >> + {
> >> + case NE: /* NE, Z == 0. */
> >> + return inverse ? AARCH64_CC_Z : 0;
> >> + case EQ: /* EQ, Z == 1. */
> >> + return inverse ? 0 : AARCH64_CC_Z;
> >> + case LE: /* LE, !(Z == 0 && N == V). */
> >> + return inverse ? AARCH64_CC_N | AARCH64_CC_V : AARCH64_CC_Z;
> >> + case GT: /* GT, Z == 0 && N == V. */
> >> + return inverse ? AARCH64_CC_Z : AARCH64_CC_N | AARCH64_CC_V;
> >> + case LT: /* LT, N != V. */
> >> + return inverse ? AARCH64_CC_N | AARCH64_CC_V : AARCH64_CC_N;
> >> + case GE: /* GE, N == V. */
> >> + return inverse ? AARCH64_CC_N : AARCH64_CC_N | AARCH64_CC_V;
> >> + case LEU: /* LS, !(C == 1 && Z == 0). */
> >> + return inverse ? AARCH64_CC_C: AARCH64_CC_Z;
> >> + case GTU: /* HI, C ==1 && Z == 0. */
> >> + return inverse ? AARCH64_CC_Z : AARCH64_CC_C;
> >> + case LTU: /* CC, C == 0. */
> >> + return inverse ? AARCH64_CC_C : 0;
> >> + case GEU: /* CS, C == 1. */
> >> + return inverse ? 0 : AARCH64_CC_C;
> >> + default:
> >> + gcc_unreachable ();
> >> + return 0;
> >> + }
> >> +}
> >> +
> >
> > I'm not overly fond of this, since "code" doesn't map 1-1. It needs
> > the context of a mode to provide a unique mapping.
> >
> > I think it would be better to rearrange the existing aarch64_cond_code
> > enum such that AARCH64_NE et al are meaningful wrt NZCV. Then you can
> > use
> > aarch64_get_condition_code_1 to get this mapping.
>
> Slight mistake in the advice here. I think you should use
> aarch64_get_conditional_code_1 to get an aarch64_cond_code, and use that
> to index an array to get the nzcv bits.
Thanks for the comments. Patch is updated.
> Further, does it actually make sense to store both nzcv and its inverse,
or
> does it work to use nzcv and ~nzcv?
Flag GE checks N == V and LT checks N != V. We can no distinguish them with
nzcv and ~nzcv
Since aarch64_output_ccmp is removed as your comments, the patch is combined
with [PATCH, 8/10] aarch64: ccmp insn patterns. Please find the updated
patch in later email.
Thanks!
-Zhenqiang