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[PATCH] rs6000: Use xori for HTM builtins and vector compares
- From: Segher Boessenkool <segher at kernel dot crashing dot org>
- To: gcc-patches at gcc dot gnu dot org
- Cc: dje dot gcc at gmail dot com, Segher Boessenkool <segher at kernel dot crashing dot org>
- Date: Tue, 9 Sep 2014 12:29:03 -0700
- Subject: [PATCH] rs6000: Use xori for HTM builtins and vector compares
- Authentication-results: sourceware.org; auth=none
These patterns use subfic now. subfic clobbers the carry. Other code
already preferably uses xor. Let's do the same here.
Bootstrapped and tested as usual, no regressions. Is this okay to apply?
Segher
2014-09-09 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/htm.md (tabort, tabortdc, tabortdci, tabortwc,
tabortwci, tbegin, tcheck, tend, trechkpt, treclaim, tsr): Use xor
instead of minus.
* config/rs6000/vector.md (cr6_test_for_zero_reverse,
cr6_test_for_lt_reverse): Ditto.
---
gcc/config/rs6000/htm.md | 33 ++++++++++++++++++++++-----------
gcc/config/rs6000/vector.md | 8 ++++++--
2 files changed, 28 insertions(+), 13 deletions(-)
diff --git a/gcc/config/rs6000/htm.md b/gcc/config/rs6000/htm.md
index 140212b..03948b1 100644
--- a/gcc/config/rs6000/htm.md
+++ b/gcc/config/rs6000/htm.md
@@ -55,7 +55,8 @@ (define_expand "tabort"
(eq:SI (match_dup 2)
(const_int 0)))
(set (match_operand:SI 0 "int_reg_operand" "")
- (minus:SI (const_int 1) (match_dup 3)))]
+ (xor:SI (match_dup 3)
+ (const_int 1)))]
"TARGET_HTM"
{
operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);
@@ -81,7 +82,8 @@ (define_expand "tabortdc"
(eq:SI (match_dup 4)
(const_int 0)))
(set (match_operand:SI 0 "int_reg_operand" "")
- (minus:SI (const_int 1) (match_dup 5)))]
+ (xor:SI (match_dup 5)
+ (const_int 1)))]
"TARGET_HTM"
{
operands[4] = gen_rtx_REG (CCmode, CR0_REGNO);
@@ -109,7 +111,8 @@ (define_expand "tabortdci"
(eq:SI (match_dup 4)
(const_int 0)))
(set (match_operand:SI 0 "int_reg_operand" "")
- (minus:SI (const_int 1) (match_dup 5)))]
+ (xor:SI (match_dup 5)
+ (const_int 1)))]
"TARGET_HTM"
{
operands[4] = gen_rtx_REG (CCmode, CR0_REGNO);
@@ -137,7 +140,8 @@ (define_expand "tabortwc"
(eq:SI (match_dup 4)
(const_int 0)))
(set (match_operand:SI 0 "int_reg_operand" "")
- (minus:SI (const_int 1) (match_dup 5)))]
+ (xor:SI (match_dup 5)
+ (const_int 1)))]
"TARGET_HTM"
{
operands[4] = gen_rtx_REG (CCmode, CR0_REGNO);
@@ -165,7 +169,8 @@ (define_expand "tabortwci"
(eq:SI (match_dup 4)
(const_int 0)))
(set (match_operand:SI 0 "int_reg_operand" "")
- (minus:SI (const_int 1) (match_dup 5)))]
+ (xor:SI (match_dup 5)
+ (const_int 1)))]
"TARGET_HTM"
{
operands[4] = gen_rtx_REG (CCmode, CR0_REGNO);
@@ -209,7 +214,8 @@ (define_expand "tbegin"
(eq:SI (match_dup 2)
(const_int 0)))
(set (match_operand:SI 0 "int_reg_operand" "")
- (minus:SI (const_int 1) (match_dup 3)))]
+ (xor:SI (match_dup 3)
+ (const_int 1)))]
"TARGET_HTM"
{
operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);
@@ -233,7 +239,8 @@ (define_expand "tcheck"
(eq:SI (match_dup 2)
(const_int 0)))
(set (match_operand:SI 0 "int_reg_operand" "")
- (minus:SI (const_int 1) (match_dup 3)))]
+ (xor:SI (match_dup 3)
+ (const_int 1)))]
"TARGET_HTM"
{
operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);
@@ -257,7 +264,8 @@ (define_expand "tend"
(eq:SI (match_dup 2)
(const_int 0)))
(set (match_operand:SI 0 "int_reg_operand" "")
- (minus:SI (const_int 1) (match_dup 3)))]
+ (xor:SI (match_dup 3)
+ (const_int 1)))]
"TARGET_HTM"
{
operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);
@@ -281,7 +289,8 @@ (define_expand "trechkpt"
(eq:SI (match_dup 1)
(const_int 0)))
(set (match_operand:SI 0 "int_reg_operand" "")
- (minus:SI (const_int 1) (match_dup 2)))]
+ (xor:SI (match_dup 2)
+ (const_int 1)))]
"TARGET_HTM"
{
operands[1] = gen_rtx_REG (CCmode, CR0_REGNO);
@@ -305,7 +314,8 @@ (define_expand "treclaim"
(eq:SI (match_dup 2)
(const_int 0)))
(set (match_operand:SI 0 "int_reg_operand" "")
- (minus:SI (const_int 1) (match_dup 3)))]
+ (xor:SI (match_dup 3)
+ (const_int 1)))]
"TARGET_HTM"
{
operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);
@@ -329,7 +339,8 @@ (define_expand "tsr"
(eq:SI (match_dup 2)
(const_int 0)))
(set (match_operand:SI 0 "int_reg_operand" "")
- (minus:SI (const_int 1) (match_dup 3)))]
+ (xor:SI (match_dup 3)
+ (const_int 1)))]
"TARGET_HTM"
{
operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index bfae244..237724e 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -686,7 +686,9 @@ (define_expand "cr6_test_for_zero_reverse"
[(set (match_operand:SI 0 "register_operand" "=r")
(eq:SI (reg:CC 74)
(const_int 0)))
- (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
+ (set (match_dup 0)
+ (xor:SI (match_dup 0)
+ (const_int 1)))]
"TARGET_ALTIVEC || TARGET_VSX"
"")
@@ -701,7 +703,9 @@ (define_expand "cr6_test_for_lt_reverse"
[(set (match_operand:SI 0 "register_operand" "=r")
(lt:SI (reg:CC 74)
(const_int 0)))
- (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
+ (set (match_dup 0)
+ (xor:SI (match_dup 0)
+ (const_int 1)))]
"TARGET_ALTIVEC || TARGET_VSX"
"")
--
1.8.1.4