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Re: [PATCH] SPARC: add mcpu=leon3v7 target

Hi Joel,

Yes an update is required. If/when I get positive comments on the mcpu=leon3v7 patch I will suggest a new updated multilib patch and a RTEMS LEON3 BSP build configuration change.
I have tested the mcpu=leon3v7 patch with RTEMS leon3 BSP generating V7 instructions, and ngmp generating V8 instructions to check that I haven't broken anything. The instructions generated in the both cases are good, and the RTEMS single-core test-suite runs on both GR712RC and NGFP hardware successfully (apart from the already known two failures of course). 

Regards,
Daniel Hellstrom

On 08/20/2014 05:05 PM, Joel Sherrill wrote:

Daniel,

Does this mean that Sebastian's patch to add a leon3 multilib for
sparc-rtems
needs to be augmented to handled leon3v7? Or does it need to map to a
regular v7 library?

It just seems like the multilibs should have been touched somehow.

--joel
On 8/20/2014 10:01 AM, Daniel Hellstrom wrote:

The LEON3/4 soft-core CPU has support for both SPARCv7 and SPARCv8 that
is configurable at design time. The majority of the LEON3 ASICs are v8
compatible, however when designing an as small LEON3 as possible, v7
without FPU is frequently used.

The current GCC leon3 support implies the SPARCv8 instruction set
which is not compatible with SPARCv7. Relying on the standard SPARCv7
(-mcpu=v7) target for a LEON3-V7 is not feasible since the atomic
instruction (CAS) can not be generated by standard v7 target. This
is also a problem for binaries aiming to be compatible with all LEON3/4
processors.

  * config.gcc (sparc*-*-*): Accept mcpu=leon3v7 processor
  * doc/invoke.texi (SPARC options): add mcpu=leon3v7 comment
  * config/sparc/leon.md (leon3_load, leon_store, leon_fp_*):
    handle leon3v7 as leon3
  * config/sparc/sparc-opts.h (enum processor_type): Add PROCESSOR_LEON3V7
  * config/sparc/sparc.c (sparc_option_override): add leon3v7 support
  * config/sparc/sparc.h (TARGET_CPU_leon3v7): new define
  * config/sparc/sparc.md (cpu): add leon3v7
  * config/sparc/sparc.opt (enum processor_type): Add leon3v7
---
  gcc/config.gcc                |    5 ++++-
  gcc/config/sparc/leon.md      |   14 +++++++-------
  gcc/config/sparc/sparc-opts.h |    1 +
  gcc/config/sparc/sparc.c      |    3 +++
  gcc/config/sparc/sparc.h      |   38 +++++++++++++++++++++++---------------
  gcc/config/sparc/sparc.md     |    1 +
  gcc/config/sparc/sparc.opt    |    3 +++
  gcc/doc/invoke.texi           |   16 ++++++++--------
  8 files changed, 50 insertions(+), 31 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 605efc0..199e387 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -3065,6 +3065,9 @@ if test x$with_cpu = x ; then
  	*-leon[3-9]*)
  	  with_cpu=leon3
  	  ;;
+	*-leon[3-9]v7*)
+	  with_cpu=leon3v7
+	  ;;
  	*)
  	  with_cpu="`echo ${target} | sed 's/-.*$//'`"
  	  ;;
@@ -3749,7 +3752,7 @@ case "${target}" in
  			case ${val} in
  			"" | sparc | sparcv9 | sparc64 \
  			| v7 | cypress \
-			| v8 | supersparc | hypersparc | leon | leon3 \
+			| v8 | supersparc | hypersparc | leon | leon3 | leon3v7 \
  			| sparclite | f930 | f934 | sparclite86x \
  			| sparclet | tsc701 \
  			| v9 | ultrasparc | ultrasparc3 | niagara | niagara2 \
diff --git a/gcc/config/sparc/leon.md b/gcc/config/sparc/leon.md
index b511397..e8050fa 100644
--- a/gcc/config/sparc/leon.md
+++ b/gcc/config/sparc/leon.md
@@ -29,11 +29,11 @@
;; Use a double reservation to work around the load pipeline hazard on UT699. 
  (define_insn_reservation "leon3_load" 1
-  (and (eq_attr "cpu" "leon3") (eq_attr "type" "load,sload"))
+  (and (eq_attr "cpu" "leon3,leon3v7") (eq_attr "type" "load,sload"))
    "leon_memory*2")
(define_insn_reservation "leon_store" 2 
-  (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "store"))
+  (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "store"))
    "leon_memory*2")
;; This describes Gaisler Research's FPU 
@@ -44,21 +44,21 @@
  (define_cpu_unit "grfpu_ds" "grfpu")
(define_insn_reservation "leon_fp_alu" 4 
-  (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fp,fpcmp,fpmul"))
+  (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fp,fpcmp,fpmul"))
    "grfpu_alu, nothing*3")
(define_insn_reservation "leon_fp_divs" 16 
-  (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpdivs"))
+  (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpdivs"))
    "grfpu_ds*14, nothing*2")
(define_insn_reservation "leon_fp_divd" 17 
-  (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpdivd"))
+  (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpdivd"))
    "grfpu_ds*15, nothing*2")
(define_insn_reservation "leon_fp_sqrts" 24 
-  (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpsqrts"))
+  (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpsqrts"))
    "grfpu_ds*22, nothing*2")
(define_insn_reservation "leon_fp_sqrtd" 25 
-  (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpsqrtd"))
+  (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpsqrtd"))
    "grfpu_ds*23, nothing*2")
diff --git a/gcc/config/sparc/sparc-opts.h b/gcc/config/sparc/sparc-opts.h
index b5e9761..c35bee4 100644
--- a/gcc/config/sparc/sparc-opts.h
+++ b/gcc/config/sparc/sparc-opts.h
@@ -31,6 +31,7 @@ enum processor_type {
    PROCESSOR_HYPERSPARC,
    PROCESSOR_LEON,
    PROCESSOR_LEON3,
+  PROCESSOR_LEON3V7,
    PROCESSOR_SPARCLITE,
    PROCESSOR_F930,
    PROCESSOR_F934,
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index e9b2bcf..7f3c43e 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -1125,6 +1125,7 @@ sparc_option_override (void)
      { TARGET_CPU_hypersparc, PROCESSOR_HYPERSPARC },
      { TARGET_CPU_leon, PROCESSOR_LEON },
      { TARGET_CPU_leon3, PROCESSOR_LEON3 },
+    { TARGET_CPU_leon3v7, PROCESSOR_LEON3V7 },
      { TARGET_CPU_sparclite, PROCESSOR_F930 },
      { TARGET_CPU_sparclite86x, PROCESSOR_SPARCLITE86X },
      { TARGET_CPU_sparclet, PROCESSOR_TSC701 },
@@ -1153,6 +1154,7 @@ sparc_option_override (void)
      { "hypersparc",	MASK_ISA, MASK_V8|MASK_FPU },
      { "leon",		MASK_ISA, MASK_V8|MASK_LEON|MASK_FPU },
      { "leon3",		MASK_ISA, MASK_V8|MASK_LEON3|MASK_FPU },
+    { "leon3v7",	MASK_ISA, MASK_LEON3|MASK_FPU },
      { "sparclite",	MASK_ISA, MASK_SPARCLITE },
      /* The Fujitsu MB86930 is the original sparclite chip, with no FPU.  */
      { "f930",		MASK_ISA|MASK_FPU, MASK_SPARCLITE },
@@ -1405,6 +1407,7 @@ sparc_option_override (void)
        sparc_costs = &leon_costs;
        break;
      case PROCESSOR_LEON3:
+    case PROCESSOR_LEON3V7:
        sparc_costs = &leon3_costs;
        break;
      case PROCESSOR_SPARCLET:
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index d96c1b6..0a7bcb7 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -137,21 +137,22 @@ extern enum cmodel sparc_cmodel;
  #define TARGET_CPU_hypersparc	3
  #define TARGET_CPU_leon		4
  #define TARGET_CPU_leon3	5
-#define TARGET_CPU_sparclite	6
-#define TARGET_CPU_f930		6       /* alias */
-#define TARGET_CPU_f934		6       /* alias */
-#define TARGET_CPU_sparclite86x	7
-#define TARGET_CPU_sparclet	8
-#define TARGET_CPU_tsc701	8       /* alias */
-#define TARGET_CPU_v9		9	/* generic v9 implementation */
-#define TARGET_CPU_sparcv9	9	/* alias */
-#define TARGET_CPU_sparc64	9	/* alias */
-#define TARGET_CPU_ultrasparc	10
-#define TARGET_CPU_ultrasparc3	11
-#define TARGET_CPU_niagara	12
-#define TARGET_CPU_niagara2	13
-#define TARGET_CPU_niagara3	14
-#define TARGET_CPU_niagara4	15
+#define TARGET_CPU_leon3v7	6
+#define TARGET_CPU_sparclite	7
+#define TARGET_CPU_f930		7       /* alias */
+#define TARGET_CPU_f934		7       /* alias */
+#define TARGET_CPU_sparclite86x	8
+#define TARGET_CPU_sparclet	9
+#define TARGET_CPU_tsc701	9       /* alias */
+#define TARGET_CPU_v9		10	/* generic v9 implementation */
+#define TARGET_CPU_sparcv9	10	/* alias */
+#define TARGET_CPU_sparc64	10	/* alias */
+#define TARGET_CPU_ultrasparc	11
+#define TARGET_CPU_ultrasparc3	12
+#define TARGET_CPU_niagara	13
+#define TARGET_CPU_niagara2	14
+#define TARGET_CPU_niagara3	15
+#define TARGET_CPU_niagara4	16
#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ 
   || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
@@ -239,6 +240,11 @@ extern enum cmodel sparc_cmodel;
  #define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG
  #endif
+#if TARGET_CPU_DEFAULT == TARGET_CPU_leon3v7 
+#define CPP_CPU32_DEFAULT_SPEC "-D__leon__"
+#define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG
+#endif
+
  #endif
#if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) 
@@ -285,6 +291,7 @@ extern enum cmodel sparc_cmodel;
  %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
  %{mcpu=leon:-D__leon__ -D__sparc_v8__} \
  %{mcpu=leon3:-D__leon__ -D__sparc_v8__} \
+%{mcpu=leon3v7:-D__leon__} \
  %{mcpu=v9:-D__sparc_v9__} \
  %{mcpu=ultrasparc:-D__sparc_v9__} \
  %{mcpu=ultrasparc3:-D__sparc_v9__} \
@@ -334,6 +341,7 @@ extern enum cmodel sparc_cmodel;
  %{mcpu=hypersparc:-Av8} \
  %{mcpu=leon:" AS_LEON_FLAG "} \
  %{mcpu=leon3:" AS_LEON_FLAG "} \
+%{mcpu=leon3v7:" AS_LEON_FLAG "} \
  %{mv8plus:-Av8plus} \
  %{mcpu=v9:-Av9} \
  %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 174a6b1..b074367 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -215,6 +215,7 @@
     hypersparc,
     leon,
     leon3,
+   leon3v7,
     sparclite,
     f930,
     f934,
diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt
index 3ccd54f..ac9e6b1 100644
--- a/gcc/config/sparc/sparc.opt
+++ b/gcc/config/sparc/sparc.opt
@@ -149,6 +149,9 @@ EnumValue
  Enum(sparc_processor_type) String(leon3) Value(PROCESSOR_LEON3)
EnumValue 
+Enum(sparc_processor_type) String(leon3v7) Value(PROCESSOR_LEON3V7)
+
+EnumValue
  Enum(sparc_processor_type) String(sparclite) Value(PROCESSOR_SPARCLITE)
EnumValue 
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 508bbb4..21b122a 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -19606,8 +19606,8 @@ the rules of the ABI@.
  Set the instruction set, register set, and instruction scheduling parameters
  for machine type @var{cpu_type}.  Supported values for @var{cpu_type} are
  @samp{v7}, @samp{cypress}, @samp{v8}, @samp{supersparc}, @samp{hypersparc},
-@samp{leon}, @samp{leon3}, @samp{sparclite}, @samp{f930}, @samp{f934},
-@samp{sparclite86x}, @samp{sparclet}, @samp{tsc701}, @samp{v9},
+@samp{leon}, @samp{leon3}, @samp{leon3v7}, @samp{sparclite}, @samp{f930},
+@samp{f934}, @samp{sparclite86x}, @samp{sparclet}, @samp{tsc701}, @samp{v9},
  @samp{ultrasparc}, @samp{ultrasparc3}, @samp{niagara}, @samp{niagara2},
  @samp{niagara3} and @samp{niagara4}.
@@ -19625,7 +19625,7 @@ implementations. @table @asis 
  @item v7
-cypress
+cypress, leon3v7
@item v8 
  supersparc, hypersparc, leon, leon3
@@ -19690,11 +19690,11 @@ option @option{-mcpu=@var{cpu_type}} does.
  The same values for @option{-mcpu=@var{cpu_type}} can be used for
  @option{-mtune=@var{cpu_type}}, but the only useful values are those
  that select a particular CPU implementation.  Those are @samp{cypress},
-@samp{supersparc}, @samp{hypersparc}, @samp{leon}, @samp{leon3}, @samp{f930},
-@samp{f934}, @samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc},
-@samp{ultrasparc3}, @samp{niagara}, @samp{niagara2}, @samp{niagara3} and
-@samp{niagara4}.  With native Solaris and GNU/Linux toolchains, @samp{native}
-can also be used.
+@samp{supersparc}, @samp{hypersparc}, @samp{leon}, @samp{leon3},
+@samp{leon3v7}, @samp{f930}, @samp{f934}, @samp{sparclite86x}, @samp{tsc701},
+@samp{ultrasparc}, @samp{ultrasparc3}, @samp{niagara}, @samp{niagara2},
+@samp{niagara3} and @samp{niagara4}.  With native Solaris and GNU/Linux
+toolchains, @samp{native} can also be used.
@item -mv8plus 
  @itemx -mno-v8plus
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