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[PATCH][ARM][1/7] Convert FP mnemonics to UAL | mov patterns


Hi all,

In this patch the move patterns are updated.
For the fconst case where the constant is encoded in a decimal
representation before going into the immediate field of the assembly
instruction UAL syntax allows for the real operand to be output directly
and leaves the assembler to do the encoding.
This simplifies the logic in arm_print_operand a bit.

fp_immediate_constant is deleted and it seems that the function was not
meant to be used anyway (it returned "0" for all inputs!)

Ok for trunk?

Thanks,
Kyrill

2014-08-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     * config/arm/arm.c (output_move_vfp): Use UAL syntax for load/store
     multiple.
     (arm_print_operand): Don't convert real values to decimal
     representation in default case.
     (fp_immediate_constant): Delete.
     * config/arm/arm-protos.h (fp_immediate_constant): Likewise.
     * config/arm/vfp.md (*arm_movsi_vfp): Convert to VFP moves to UAL
     syntax.
     (*thumb2_movsi_vfp): Likewise.
     (*movdi_vfp): Likewise.
     (*movdi_vfp_cortexa8): Likewise.
     (*movhf_vfp_neon): Likewise.
     (*movhf_vfp): Likewise.
     (*movsf_vfp): Likewise.
     (*thumb2_movsf_vfp): Likewise.
     (*movdf_vfp): Likewise.
     (*thumb2_movdf_vfp): Likewise.
     (*movsfcc_vfp): Likewise.
     (*thumb2_movsfcc_vfp): Likewise.
     (*movdfcc_vfp): Likewise.
     (*thumb2_movdfcc_vfp): Likewise.

2014-08-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     * gcc.target/arm/pr51835.c: Update expected assembly.
     * gcc.target/arm/vfp-1.c: Likewise.
     * gcc.target/arm/vfp-ldmdbd.c: Likewise.
     * gcc.target/arm/vfp-ldmdbs.c: Likewise.
     * gcc.target/arm/vfp-ldmiad.c: Likewise.
     * gcc.target/arm/vfp-ldmias.c: Likewise.
     * gcc.target/arm/vfp-stmdbd.c: Likewise.
     * gcc.target/arm/vfp-stmdbs.c: Likewise.
     * gcc.target/arm/vfp-stmiad.c: Likewise.
     * gcc.target/arm/vfp-stmias.c: Likewise.
commit d4f1dd4f8198c8e6134019adfae3730737360946
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Thu Jul 17 09:44:06 2014 +0100

    [ARM][1/n] Convert FP mnemonics to UAL | mov patterns

diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 1c887aa..8d9f359 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -126,7 +126,6 @@ extern int arm_max_const_double_inline_cost (void);
 extern int arm_const_double_inline_cost (rtx);
 extern bool arm_const_double_by_parts (rtx);
 extern bool arm_const_double_by_immediates (rtx);
-extern const char *fp_immediate_constant (rtx);
 extern void arm_emit_call_insn (rtx, rtx, bool);
 extern const char *output_call (rtx *);
 extern const char *output_call_mem (rtx *);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index ffa91eb..61e4adb 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -17534,24 +17534,7 @@ arm_reorg (void)
 
 /* Routines to output assembly language.  */
 
-/* If the rtx is the correct value then return the string of the number.
-   In this way we can ensure that valid double constants are generated even
-   when cross compiling.  */
-const char *
-fp_immediate_constant (rtx x)
-{
-  REAL_VALUE_TYPE r;
-
-  if (!fp_consts_inited)
-    init_fp_table ();
-
-  REAL_VALUE_FROM_CONST_DOUBLE (r, x);
-
-  gcc_assert (REAL_VALUES_EQUAL (r, value_fp0));
-  return "0";
-}
-
-/* As for fp_immediate_constant, but value is passed directly, not in rtx.  */
+/* Return string representation of passed in real value.  */
 static const char *
 fp_const_from_val (REAL_VALUE_TYPE *r)
 {
@@ -18467,19 +18450,19 @@ output_move_vfp (rtx *operands)
   switch (GET_CODE (addr))
     {
     case PRE_DEC:
-      templ = "f%smdb%c%%?\t%%0!, {%%%s1}%s";
+      templ = "v%smdb%%?.%s\t%%0!, {%%%s1}%s";
       ops[0] = XEXP (addr, 0);
       ops[1] = reg;
       break;
 
     case POST_INC:
-      templ = "f%smia%c%%?\t%%0!, {%%%s1}%s";
+      templ = "v%smia%%?.%s\t%%0!, {%%%s1}%s";
       ops[0] = XEXP (addr, 0);
       ops[1] = reg;
       break;
 
     default:
-      templ = "f%s%c%%?\t%%%s0, %%1%s";
+      templ = "v%sr%%?.%s\t%%%s0, %%1%s";
       ops[0] = reg;
       ops[1] = mem;
       break;
@@ -18487,7 +18470,7 @@ output_move_vfp (rtx *operands)
 
   sprintf (buff, templ,
 	   load ? "ld" : "st",
-	   dp ? 'd' : 's',
+	   dp ? "64" : "32",
 	   dp ? "P" : "",
 	   integer_p ? "\t%@ int" : "");
   output_asm_insn (buff, ops);
@@ -22132,15 +22115,12 @@ arm_print_operand (FILE *stream, rtx x, int code)
 	  break;
 
 	case CONST_DOUBLE:
-          if (TARGET_NEON)
-            {
-              char fpstr[20];
-              real_to_decimal (fpstr, CONST_DOUBLE_REAL_VALUE (x),
-			       sizeof (fpstr), 0, 1);
-              fprintf (stream, "#%s", fpstr);
-            }
-          else
-	    fprintf (stream, "#%s", fp_immediate_constant (x));
+	  {
+            char fpstr[20];
+            real_to_decimal (fpstr, CONST_DOUBLE_REAL_VALUE (x),
+			      sizeof (fpstr), 0, 1);
+            fprintf (stream, "#%s", fpstr);
+	  }
 	  break;
 
 	default:
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index ab502ad..d25505c 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -41,11 +41,11 @@ (define_insn "*arm_movsi_vfp"
     case 5:
       return \"str%?\\t%1, %0\";
     case 6:
-      return \"fmsr%?\\t%0, %1\\t%@ int\";
+      return \"vmov%?\\t%0, %1\\t%@ int\";
     case 7:
-      return \"fmrs%?\\t%0, %1\\t%@ int\";
+      return \"vmov%?\\t%0, %1\\t%@ int\";
     case 8:
-      return \"fcpys%?\\t%0, %1\\t%@ int\";
+      return \"vmov%?.f32\\t%0, %1\\t%@ int\";
     case 9: case 10:
       return output_move_vfp (operands);
     default:
@@ -87,11 +87,11 @@ (define_insn "*thumb2_movsi_vfp"
     case 8:
       return \"str%?\\t%1, %0\";
     case 9:
-      return \"fmsr%?\\t%0, %1\\t%@ int\";
+      return \"vmov%?\\t%0, %1\\t%@ int\";
     case 10:
-      return \"fmrs%?\\t%0, %1\\t%@ int\";
+      return \"vmov%?\\t%0, %1\\t%@ int\";
     case 11:
-      return \"fcpys%?\\t%0, %1\\t%@ int\";
+      return \"vmov%?.f32\\t%0, %1\\t%@ int\";
     case 12: case 13:
       return output_move_vfp (operands);
     default:
@@ -130,14 +130,14 @@ (define_insn "*movdi_vfp"
     case 6:
       return output_move_double (operands, true, NULL);
     case 7:
-      return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
+      return \"vmov%?\\t%P0, %Q1, %R1\\t%@ int\";
     case 8:
-      return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
+      return \"vmov%?\\t%Q0, %R0, %P1\\t%@ int\";
     case 9:
       if (TARGET_VFP_SINGLE)
-	return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
+	return \"vmov%?.f32\\t%0, %1\\t%@ int\;vmov%?.f32\\t%p0, %p1\\t%@ int\";
       else
-	return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
+	return \"vmov%?.f64\\t%P0, %P1\\t%@ int\";
     case 10: case 11:
       return output_move_vfp (operands);
     default:
@@ -181,11 +181,11 @@ (define_insn "*movdi_vfp_cortexa8"
     case 6:
       return output_move_double (operands, true, NULL);
     case 7:
-      return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
+      return \"vmov%?\\t%P0, %Q1, %R1\\t%@ int\";
     case 8:
-      return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
+      return \"vmov%?\\t%Q0, %R0, %P1\\t%@ int\";
     case 9:
-      return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
+      return \"vmov%?.f64\\t%P0, %P1\\t%@ int\";
     case 10: case 11:
       return output_move_vfp (operands);
     default:
@@ -229,13 +229,13 @@ (define_insn "*movhf_vfp_neon"
     case 3:     /* memory from ARM register */
       return \"strh\\t%1, %0\\t%@ __fp16\";
     case 4:	/* S register from S register */
-      return \"fcpys\\t%0, %1\";
+      return \"vmov.f32\\t%0, %1\";
     case 5:	/* ARM register from ARM register */
       return \"mov\\t%0, %1\\t%@ __fp16\";
     case 6:	/* S register from ARM register */
-      return \"fmsr\\t%0, %1\";
+      return \"vmov\\t%0, %1\";
     case 7:	/* ARM register from S register */
-      return \"fmrs\\t%0, %1\";
+      return \"vmov\\t%0, %1\";
     case 8:	/* ARM register from constant */
       {
         REAL_VALUE_TYPE r;
@@ -280,13 +280,13 @@ (define_insn "*movhf_vfp"
     case 1:     /* memory from ARM register */
       return \"strh\\t%1, %0\\t%@ __fp16\";
     case 2:	/* S register from S register */
-      return \"fcpys\\t%0, %1\";
+      return \"vmov.f32\\t%0, %1\";
     case 3:	/* ARM register from ARM register */
       return \"mov\\t%0, %1\\t%@ __fp16\";
     case 4:	/* S register from ARM register */
-      return \"fmsr\\t%0, %1\";
+      return \"vmov\\t%0, %1\";
     case 5:	/* ARM register from S register */
-      return \"fmrs\\t%0, %1\";
+      return \"vmov\\t%0, %1\";
     case 6:	/* ARM register from constant */
       {
         REAL_VALUE_TYPE r;
@@ -322,7 +322,7 @@ (define_insn "*movhf_vfp"
 
 (define_insn "*movsf_vfp"
   [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t ,t  ,Uv,r ,m,t,r")
-	(match_operand:SF 1 "general_operand"	   " ?r,t,Dv,UvE,t, mE,r,t,r"))]
+        (match_operand:SF 1 "general_operand"	   " ?r,t,Dv,UvE,t, mE,r,t,r"))]
   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
    && (   s_register_operand (operands[0], SFmode)
        || s_register_operand (operands[1], SFmode))"
@@ -330,11 +330,11 @@ (define_insn "*movsf_vfp"
   switch (which_alternative)
     {
     case 0:
-      return \"fmsr%?\\t%0, %1\";
+      return \"vmov%?\\t%0, %1\";
     case 1:
-      return \"fmrs%?\\t%0, %1\";
+      return \"vmov%?\\t%0, %1\";
     case 2:
-      return \"fconsts%?\\t%0, #%G1\";
+      return \"vmov%?.f32\\t%0, %1\";
     case 3: case 4:
       return output_move_vfp (operands);
     case 5:
@@ -342,7 +342,7 @@ (define_insn "*movsf_vfp"
     case 6:
       return \"str%?\\t%1, %0\\t%@ float\";
     case 7:
-      return \"fcpys%?\\t%0, %1\";
+      return \"vmov%?.f32\\t%0, %1\";
     case 8:
       return \"mov%?\\t%0, %1\\t%@ float\";
     default:
@@ -366,11 +366,11 @@ (define_insn "*thumb2_movsf_vfp"
   switch (which_alternative)
     {
     case 0:
-      return \"fmsr%?\\t%0, %1\";
+      return \"vmov%?\\t%0, %1\";
     case 1:
-      return \"fmrs%?\\t%0, %1\";
+      return \"vmov%?\\t%0, %1\";
     case 2:
-      return \"fconsts%?\\t%0, #%G1\";
+      return \"vmov%?.f32\\t%0, %1\";
     case 3: case 4:
       return output_move_vfp (operands);
     case 5:
@@ -378,7 +378,7 @@ (define_insn "*thumb2_movsf_vfp"
     case 6:
       return \"str%?\\t%1, %0\\t%@ float\";
     case 7:
-      return \"fcpys%?\\t%0, %1\";
+      return \"vmov%?.f32\\t%0, %1\";
     case 8:
       return \"mov%?\\t%0, %1\\t%@ float\";
     default:
@@ -406,21 +406,21 @@ (define_insn "*movdf_vfp"
     switch (which_alternative)
       {
       case 0:
-	return \"fmdrr%?\\t%P0, %Q1, %R1\";
+	return \"vmov%?\\t%P0, %Q1, %R1\";
       case 1:
-	return \"fmrrd%?\\t%Q0, %R0, %P1\";
+	return \"vmov%?\\t%Q0, %R0, %P1\";
       case 2:
 	gcc_assert (TARGET_VFP_DOUBLE);
-        return \"fconstd%?\\t%P0, #%G1\";
+        return \"vmov%?.f64\\t%P0, %1\";
       case 3: case 4:
 	return output_move_vfp (operands);
       case 5: case 6:
 	return output_move_double (operands, true, NULL);
       case 7:
 	if (TARGET_VFP_SINGLE)
-	  return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
+	  return \"vmov%?.f32\\t%0, %1\;vmov%?.f32\\t%p0, %p1\";
 	else
-	  return \"fcpyd%?\\t%P0, %P1\";
+	  return \"vmov%?.f64\\t%P0, %P1\";
       case 8:
         return \"#\";
       default:
@@ -453,21 +453,21 @@ (define_insn "*thumb2_movdf_vfp"
     switch (which_alternative)
       {
       case 0:
-	return \"fmdrr%?\\t%P0, %Q1, %R1\";
+	return \"vmov%?\\t%P0, %Q1, %R1\";
       case 1:
-	return \"fmrrd%?\\t%Q0, %R0, %P1\";
+	return \"vmov%?\\t%Q0, %R0, %P1\";
       case 2:
 	gcc_assert (TARGET_VFP_DOUBLE);
-	return \"fconstd%?\\t%P0, #%G1\";
+	return \"vmov%?.f64\\t%P0, %1\";
       case 3: case 4:
 	return output_move_vfp (operands);
       case 5: case 6: case 8:
 	return output_move_double (operands, true, NULL);
       case 7:
 	if (TARGET_VFP_SINGLE)
-	  return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
+	  return \"vmov%?.f32\\t%0, %1\;vmov%?.f32\\t%p0, %p1\";
 	else
-	  return \"fcpyd%?\\t%P0, %P1\";
+	  return \"vmov%?.f64\\t%P0, %P1\";
       default:
 	abort ();
       }
@@ -498,15 +498,15 @@ (define_insn "*movsfcc_vfp"
 	  (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
   "@
-   fcpys%D3\\t%0, %2
-   fcpys%d3\\t%0, %1
-   fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
-   fmsr%D3\\t%0, %2
-   fmsr%d3\\t%0, %1
-   fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
-   fmrs%D3\\t%0, %2
-   fmrs%d3\\t%0, %1
-   fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
+   vmov%D3.f32\\t%0, %2
+   vmov%d3.f32\\t%0, %1
+   vmov%D3.f32\\t%0, %2\;vmov%d3.f32\\t%0, %1
+   vmov%D3\\t%0, %2
+   vmov%d3\\t%0, %1
+   vmov%D3\\t%0, %2\;vmov%d3\\t%0, %1
+   vmov%D3\\t%0, %2
+   vmov%d3\\t%0, %1
+   vmov%D3\\t%0, %2\;vmov%d3\\t%0, %1"
    [(set_attr "conds" "use")
     (set_attr "length" "4,4,8,4,4,8,4,4,8")
     (set_attr "type" "fmov,fmov,fmov,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")]
@@ -521,15 +521,15 @@ (define_insn "*thumb2_movsfcc_vfp"
 	  (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP && !arm_restrict_it"
   "@
-   it\\t%D3\;fcpys%D3\\t%0, %2
-   it\\t%d3\;fcpys%d3\\t%0, %1
-   ite\\t%D3\;fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
-   it\\t%D3\;fmsr%D3\\t%0, %2
-   it\\t%d3\;fmsr%d3\\t%0, %1
-   ite\\t%D3\;fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
-   it\\t%D3\;fmrs%D3\\t%0, %2
-   it\\t%d3\;fmrs%d3\\t%0, %1
-   ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
+   it\\t%D3\;vmov%D3.f32\\t%0, %2
+   it\\t%d3\;vmov%d3.f32\\t%0, %1
+   ite\\t%D3\;vmov%D3.f32\\t%0, %2\;vmov%d3.f32\\t%0, %1
+   it\\t%D3\;vmov%D3\\t%0, %2
+   it\\t%d3\;vmov%d3\\t%0, %1
+   ite\\t%D3\;vmov%D3\\t%0, %2\;vmov%d3\\t%0, %1
+   it\\t%D3\;vmov%D3\\t%0, %2
+   it\\t%d3\;vmov%d3\\t%0, %1
+   ite\\t%D3\;vmov%D3\\t%0, %2\;vmov%d3\\t%0, %1"
    [(set_attr "conds" "use")
     (set_attr "length" "6,6,10,6,6,10,6,6,10")
     (set_attr "type" "fmov,fmov,fmov,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")]
@@ -544,15 +544,15 @@ (define_insn "*movdfcc_vfp"
 	  (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
   "@
-   fcpyd%D3\\t%P0, %P2
-   fcpyd%d3\\t%P0, %P1
-   fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
-   fmdrr%D3\\t%P0, %Q2, %R2
-   fmdrr%d3\\t%P0, %Q1, %R1
-   fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
-   fmrrd%D3\\t%Q0, %R0, %P2
-   fmrrd%d3\\t%Q0, %R0, %P1
-   fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
+   vmov%D3.f64\\t%P0, %P2
+   vmov%d3.f64\\t%P0, %P1
+   vmov%D3.f64\\t%P0, %P2\;vmov%d3.f64\\t%P0, %P1
+   vmov%D3\\t%P0, %Q2, %R2
+   vmov%d3\\t%P0, %Q1, %R1
+   vmov%D3\\t%P0, %Q2, %R2\;vmov%d3\\t%P0, %Q1, %R1
+   vmov%D3\\t%Q0, %R0, %P2
+   vmov%d3\\t%Q0, %R0, %P1
+   vmov%D3\\t%Q0, %R0, %P2\;vmov%d3\\t%Q0, %R0, %P1"
    [(set_attr "conds" "use")
     (set_attr "length" "4,4,8,4,4,8,4,4,8")
     (set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcr,f_mrrc,f_mrrc,f_mrrc")]
@@ -567,15 +567,15 @@ (define_insn "*thumb2_movdfcc_vfp"
 	  (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && !arm_restrict_it"
   "@
-   it\\t%D3\;fcpyd%D3\\t%P0, %P2
-   it\\t%d3\;fcpyd%d3\\t%P0, %P1
-   ite\\t%D3\;fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
-   it\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2
-   it\t%d3\;fmdrr%d3\\t%P0, %Q1, %R1
-   ite\\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
-   it\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2
-   it\t%d3\;fmrrd%d3\\t%Q0, %R0, %P1
-   ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
+   it\\t%D3\;vmov%D3.f64\\t%P0, %P2
+   it\\t%d3\;vmov%d3.f64\\t%P0, %P1
+   ite\\t%D3\;vmov%D3.f64\\t%P0, %P2\;vmov%d3.f64\\t%P0, %P1
+   it\t%D3\;vmov%D3\\t%P0, %Q2, %R2
+   it\t%d3\;vmov%d3\\t%P0, %Q1, %R1
+   ite\\t%D3\;vmov%D3\\t%P0, %Q2, %R2\;vmov%d3\\t%P0, %Q1, %R1
+   it\t%D3\;vmov%D3\\t%Q0, %R0, %P2
+   it\t%d3\;vmov%d3\\t%Q0, %R0, %P1
+   ite\\t%D3\;vmov%D3\\t%Q0, %R0, %P2\;vmov%d3\\t%Q0, %R0, %P1"
    [(set_attr "conds" "use")
     (set_attr "length" "6,6,10,6,6,10,6,6,10")
     (set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcrr,f_mrrc,f_mrrc,f_mrrc")]
diff --git a/gcc/testsuite/gcc.target/arm/pr51835.c b/gcc/testsuite/gcc.target/arm/pr51835.c
index 6d462d9..128b9d5 100644
--- a/gcc/testsuite/gcc.target/arm/pr51835.c
+++ b/gcc/testsuite/gcc.target/arm/pr51835.c
@@ -13,5 +13,5 @@ unsigned int func2 (double d)
   return (unsigned int)d;
 }
 
-/* { dg-final { scan-assembler-times "fmrrd\[\\t \]+r0,\[\\t \]*r1,\[\\t \]*d0" 2 { target { arm_little_endian } } } } */
-/* { dg-final { scan-assembler-times "fmrrd\[\\t \]+r1,\[\\t \]*r0,\[\\t \]*d0" 2 { target { ! arm_little_endian } } } } */
+/* { dg-final { scan-assembler-times "vmov\[\\t \]+r0,\[\\t \]*r1,\[\\t \]*d0" 2 { target { arm_little_endian } } } } */
+/* { dg-final { scan-assembler-times "vmov\[\\t \]+r1,\[\\t \]*r0,\[\\t \]*d0" 2 { target { ! arm_little_endian } } } } */
diff --git a/gcc/testsuite/gcc.target/arm/vfp-1.c b/gcc/testsuite/gcc.target/arm/vfp-1.c
index d6d9c46..2355b4d 100644
--- a/gcc/testsuite/gcc.target/arm/vfp-1.c
+++ b/gcc/testsuite/gcc.target/arm/vfp-1.c
@@ -126,14 +126,14 @@ void test_convert () {
 }
 
 void test_ldst (float f[], double d[]) {
-  /* { dg-final { scan-assembler "flds.+ \\\[r0, #1020\\\]" } } */
-  /* { dg-final { scan-assembler "flds.+ \\\[r\[0-9\], #-1020\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
+  /* { dg-final { scan-assembler "vldr.32.+ \\\[r0, #1020\\\]" } } */
+  /* { dg-final { scan-assembler "vldr.32.+ \\\[r\[0-9\], #-1020\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
   /* { dg-final { scan-assembler "add.+ r0, #1024" } } */
-  /* { dg-final { scan-assembler "fsts.+ \\\[r\[0-9\]\\\]\n" } } */
+  /* { dg-final { scan-assembler "vstr.32.+ \\\[r\[0-9\]\\\]\n" } } */
   f[256] = f[255] + f[-255];
 
-  /* { dg-final { scan-assembler "fldd.+ \\\[r1, #1016\\\]" } } */
-  /* { dg-final { scan-assembler "fldd.+ \\\[r\[1-9\], #-1016\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
-  /* { dg-final { scan-assembler "fstd.+ \\\[r1, #256\\\]" } } */
+  /* { dg-final { scan-assembler "vldr.64.+ \\\[r1, #1016\\\]" } } */
+  /* { dg-final { scan-assembler "vldr.64.+ \\\[r\[1-9\], #-1016\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
+  /* { dg-final { scan-assembler "vstr.64.+ \\\[r1, #256\\\]" } } */
   d[32] = d[127] + d[-127];
 }
diff --git a/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c b/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c
index 2804714..7041579 100644
--- a/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c
+++ b/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c
@@ -13,4 +13,4 @@ foo (double *p, double a, int n)
   while (n--);
 }
 
-/* { dg-final { scan-assembler "fldmdbd" } } */
+/* { dg-final { scan-assembler "vldmdb.64" } } */
diff --git a/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c b/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c
index f5940ef..10bccf6 100644
--- a/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c
+++ b/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c
@@ -13,4 +13,4 @@ foo (float *p, float a, int n)
   while (n--);
 }
 
-/* { dg-final { scan-assembler "fldmdbs" } } */
+/* { dg-final { scan-assembler "vldmdb.32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c b/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c
index 6f05267..9c22f1f 100644
--- a/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c
+++ b/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c
@@ -13,4 +13,4 @@ foo (double *p, double a, int n)
   while (n--);
 }
 
-/* { dg-final { scan-assembler "fldmiad" } } */
+/* { dg-final { scan-assembler "vldmia.64" } } */
diff --git a/gcc/testsuite/gcc.target/arm/vfp-ldmias.c b/gcc/testsuite/gcc.target/arm/vfp-ldmias.c
index 79ad7bf..bc40451 100644
--- a/gcc/testsuite/gcc.target/arm/vfp-ldmias.c
+++ b/gcc/testsuite/gcc.target/arm/vfp-ldmias.c
@@ -13,4 +13,4 @@ foo (float *p, float a, int n)
   while (n--);
 }
 
-/* { dg-final { scan-assembler "fldmias" } } */
+/* { dg-final { scan-assembler "vldmia.32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c b/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c
index d8093d9..53383b5 100644
--- a/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c
+++ b/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c
@@ -12,4 +12,4 @@ foo (double *p, double a, double b, int n)
   while (n--);
 }
 
-/* { dg-final { scan-assembler "fstmdbd" } } */
+/* { dg-final { scan-assembler "vstmdb.64" } } */
diff --git a/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c b/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c
index bb19d90..6570def 100644
--- a/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c
+++ b/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c
@@ -12,4 +12,4 @@ foo (float *p, float a, float b, int n)
   while (n--);
 }
 
-/* { dg-final { scan-assembler "fstmdbs" } } */
+/* { dg-final { scan-assembler "vstmdb.32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/vfp-stmiad.c b/gcc/testsuite/gcc.target/arm/vfp-stmiad.c
index 1b6d22b..28e9d73 100644
--- a/gcc/testsuite/gcc.target/arm/vfp-stmiad.c
+++ b/gcc/testsuite/gcc.target/arm/vfp-stmiad.c
@@ -12,4 +12,4 @@ foo (double *p, double a, double b, int n)
   while (n--);
 }
 
-/* { dg-final { scan-assembler "fstmiad" } } */
+/* { dg-final { scan-assembler "vstmia.64" } } */
diff --git a/gcc/testsuite/gcc.target/arm/vfp-stmias.c b/gcc/testsuite/gcc.target/arm/vfp-stmias.c
index 3da6327..efa5fbe 100644
--- a/gcc/testsuite/gcc.target/arm/vfp-stmias.c
+++ b/gcc/testsuite/gcc.target/arm/vfp-stmias.c
@@ -12,4 +12,4 @@ foo (float *p, float a, float b, int n)
   while (n--);
 }
 
-/* { dg-final { scan-assembler "fstmias" } } */
+/* { dg-final { scan-assembler "vstmia.32" } } */

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