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Re: [PATCH, AArch64] Use MOVN to generate 64-bit negative immediates where sensible
- From: Richard Henderson <rth at redhat dot com>
- To: Kyrill Tkachov <kyrylo dot tkachov at arm dot com>, Richard Earnshaw <Richard dot Earnshaw at arm dot com>
- Cc: gcc-patches <gcc-patches at gcc dot gnu dot org>
- Date: Thu, 14 Aug 2014 07:31:00 -1000
- Subject: Re: [PATCH, AArch64] Use MOVN to generate 64-bit negative immediates where sensible
- Authentication-results: sourceware.org; auth=none
- References: <000001cf6ae4$059c2280$10d46780$ at bolton@arm.com> <537605FF dot 8070700 at arm dot com> <53E363C2 dot 4000405 at arm dot com> <53E37532 dot 60101 at arm dot com> <53E3779C dot 1020709 at arm dot com> <53E3D467 dot 2020509 at redhat dot com> <53EB8477 dot 80208 at arm dot com>
On 08/13/2014 05:29 AM, Kyrill Tkachov wrote:
> Is the attached patch ok? It just moves the section as you suggested. I did a
> build of the Linux kernel with and without this patch to make sure no code-gen
> was accidentally affected.
Looks good.
> We'd need to store a mapping from constant to RTXes and everytime we have a
> "cache hit" we'd have to tweak them to make sure the registers involved are
> correct. I had a quick play with this but ended up with LRA ICEs :(
You mis-understand how I meant to memoize. Have a look at how we cache
expansions for multiply in synth_mult: we don't record registers or rtx's, but
we do record the operation and arguments.
So you could consider building a trie, indexed by a hash.
struct imm_algorithm
{
HOST_WIDE_INT op1;
imm_algorithm *prev;
enum operation {
// op1 is accepted by aarch64_mov_operand.
// prev should be null.
mov,
// op1 is to be inserted at the given position
// to the value constructed by prev.
movk_48, movk_32, movk_16, movk_0,
// op1 is an arithmetic immediate to be applied
// to the value constructed by prev
add, sub,
// op1 is a logical immediate to be applied to
// the value constructed by prev
and, ior,
} code;
};
r~