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Fwd: [PATCH i386 AVX512] [14/n] Add convert to PS insn patterns.


Adding community.


---------- Forwarded message ----------
From: Kirill Yukhin <kirill.yukhin@gmail.com>
Date: Thu, Aug 14, 2014 at 4:16 PM
Subject: [PATCH i386 AVX512] [14/n] Add convert to PS insn patterns.
To: Uros Bizjak <ubizjak@gmail.com>


Hello,
This patch introduces new patterns for conversions
to PS.

Bootstrapped.
New tests on top of patch-set all pass
under simulator.

Is it ok for trunk?

gcc/
        * config/i386/i386.c: Rename ufloatv8siv8df_mask to
ufloatv8siv8df2_mask.
        * config/i386/i386.md
        (define_code_iterator any_float): New.
        (define_code_attr floatsuffix): New.
        * config/i386/sse.md
        (define_mode_iterator VF1_128_256VL): New.
        (define_mode_iterator VF2_512_256VL): New.
        (define_insn "float<si2dfmodelower><mode>2<mask_name>"):
Remove unnecessary
        TARGET check.
        (define_insn "ufloatv8siv8df<mask_name>"): Delete.
        (define_insn
"<floatsuffix>float<sseintvecmodelower><mode>2<mask_name><round_name>"):
        New.
        (define_mode_attr qq2pssuff): New.
        (define_mode_attr sselongvecmode): New.
        (define_mode_attr sselongvecmodelower): New.
        (define_mode_attr sseintvecmode3): New.
        (define_insn
"<floatsuffix>float<sselongvecmodelower><mode>2<mask_name><round_name>"):
        New.
        (define_insn "*<floatsuffix>floatv2div2sf2"): New.
        (define_insn "<floatsuffix>floatv2div2sf2_mask"): New.
        (define_insn "ufloat<si2dfmodelower><mode>2<mask_name>"): New.
        (define_insn "ufloatv2siv2df2<mask_name>"): New.

--
Thanks, K

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index da01ac6..e2eda2a 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -30036,7 +30036,7 @@ static const struct builtin_description bdesc_args[] =
   { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask,
"__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512,
UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
   { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask,
"__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN,
(int) V8DF_FTYPE_V8SI_V8DF_QI },
   { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask,
"__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN,
(int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
-  { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df_mask,
"__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512,
UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
+  { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df2_mask,
"__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512,
UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
   { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32,
"__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int)
V2DF_FTYPE_V2DF_UINT },
   { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask,
"__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN,
(int) V8DF_FTYPE_V8DF_V8DF_QI },
   { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz,
"__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z,
UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index f6351cf..e686cf6 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -883,6 +883,10 @@
 (define_code_attr fixsuffix [(fix "") (unsigned_fix "u")])
 (define_code_attr ufix_bool [(fix "false") (unsigned_fix "true")])

+;; Used in signed and unsigned float.
+(define_code_iterator any_float [float unsigned_float])
+(define_code_attr floatsuffix [(float "") (unsigned_float "u")])
+
 ;; All integer modes.
 (define_mode_iterator SWI1248x [QI HI SI DI])

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index eaf97ab..d5598d4 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -205,6 +205,9 @@
 (define_mode_iterator VF1_128_256
   [(V8SF "TARGET_AVX") V4SF])

+(define_mode_iterator VF1_128_256VL
+  [V8SF (V4SF "TARGET_AVX512VL")])
+
 ;; All DFmode vector float modes
 (define_mode_iterator VF2
   [(V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") V2DF])
@@ -216,6 +219,9 @@
 (define_mode_iterator VF2_512_256
   [(V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX")])

+(define_mode_iterator VF2_512_256VL
+  [V8DF (V4DF "TARGET_AVX512VL")])
+
 ;; All 128bit vector float modes
 (define_mode_iterator VF_128
   [V4SF (V2DF "TARGET_SSE2")])
@@ -4091,21 +4097,94 @@
 (define_insn "float<si2dfmodelower><mode>2<mask_name>"
   [(set (match_operand:VF2_512_256 0 "register_operand" "=v")
        (float:VF2_512_256 (match_operand:<si2dfmode> 1
"nonimmediate_operand" "vm")))]
-  "TARGET_AVX && <mask_mode512bit_condition>"
+  "<mask_mode512bit_condition>"
   "vcvtdq2pd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "type" "ssecvt")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "<MODE>")])

-(define_insn "ufloatv8siv8df<mask_name>"
-  [(set (match_operand:V8DF 0 "register_operand" "=v")
-       (unsigned_float:V8DF
-         (match_operand:V8SI 1 "nonimmediate_operand" "vm")))]
-  "TARGET_AVX512F"
+(define_insn "<floatsuffix>float<sseintvecmodelower><mode>2<mask_name><round_name>"
+  [(set (match_operand:VF2_AVX512VL 0 "register_operand" "=v")
+       (any_float:VF2_AVX512VL
+         (match_operand:<sseintvecmode> 1 "nonimmediate_operand" "vm")))]
+  "TARGET_AVX512DQ"
+  "vcvt<floatsuffix>qq2pd\t{<round_mask_op2>%1,
%0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
+  [(set_attr "type" "ssecvt")
+   (set_attr "prefix" "evex")
+   (set_attr "mode" "<MODE>")])
+
+;; For <floatsuffix>float<sselondveclower><mode> insn patterns
+(define_mode_attr qq2pssuff
+  [(V8SF "") (V4SF "{y}")])
+
+(define_mode_attr sselongvecmode
+  [(V8SF "V8DI") (V4SF  "V4DI")])
+
+(define_mode_attr sselongvecmodelower
+  [(V8SF "v8di") (V4SF  "v4di")])
+
+(define_mode_attr sseintvecmode3
+  [(V8SF "XI") (V4SF "OI")
+   (V8DF "OI") (V4DF "TI")])
+
+(define_insn "<floatsuffix>float<sselongvecmodelower><mode>2<mask_name><round_name>"
+  [(set (match_operand:VF1_128_256VL 0 "register_operand" "=v")
+        (any_float:VF1_128_256VL
+          (match_operand:<sselongvecmode> 1 "nonimmediate_operand"
"<round_constraint>")))]
+  "TARGET_AVX512DQ && <round_modev8sf_condition>"
+  "vcvt<floatsuffix>qq2ps<qq2pssuff>\t{<round_mask_op2>%1,
%0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
+  [(set_attr "type" "ssecvt")
+   (set_attr "prefix" "evex")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "*<floatsuffix>floatv2div2sf2"
+  [(set (match_operand:V4SF 0 "register_operand" "=v")
+    (vec_concat:V4SF
+           (any_float:V2SF (match_operand:V2DI 1 "nonimmediate_operand" "vm"))
+           (const_vector:V2SF [(const_int 0) (const_int 0)])))]
+  "TARGET_AVX512DQ && TARGET_AVX512VL"
+  "vcvt<floatsuffix>qq2ps{x}\t{%1, %0|%0, %1}"
+  [(set_attr "type" "ssecvt")
+   (set_attr "prefix" "evex")
+   (set_attr "mode" "V4SF")])
+
+(define_insn "<floatsuffix>floatv2div2sf2_mask"
+  [(set (match_operand:V4SF 0 "register_operand" "=v")
+    (vec_concat:V4SF
+        (vec_merge:V2SF
+               (any_float:V2SF (match_operand:V2DI 1
"nonimmediate_operand" "vm"))
+            (vec_select:V2SF
+                (match_operand:V4SF 2 "vector_move_operand" "0C")
+                (parallel [(const_int 0) (const_int 1)]))
+            (match_operand:QI 3 "register_operand" "Yk"))
+           (const_vector:V2SF [(const_int 0) (const_int 0)])))]
+  "TARGET_AVX512DQ && TARGET_AVX512VL"
+  "vcvt<floatsuffix>qq2ps{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
+  [(set_attr "type" "ssecvt")
+   (set_attr "prefix" "evex")
+   (set_attr "mode" "V4SF")])
+
+(define_insn "ufloat<si2dfmodelower><mode>2<mask_name>"
+  [(set (match_operand:VF2_512_256VL 0 "register_operand" "=v")
+       (unsigned_float:VF2_512_256VL
+         (match_operand:<si2dfmode> 1 "nonimmediate_operand" "vm")))]
+   "TARGET_AVX512F"
+   "vcvtudq2pd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+   [(set_attr "type" "ssecvt")
+    (set_attr "prefix" "evex")
+    (set_attr "mode" "<MODE>")])
+
+(define_insn "ufloatv2siv2df2<mask_name>"
+  [(set (match_operand:V2DF 0 "register_operand" "=v")
+       (unsigned_float:V2DF
+         (vec_select:V2SI
+           (match_operand:V4SI 1 "nonimmediate_operand" "vm")
+           (parallel [(const_int 0) (const_int 1)]))))]
+  "TARGET_AVX512VL"
   "vcvtudq2pd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "type" "ssecvt")
    (set_attr "prefix" "evex")
-   (set_attr "mode" "V8DF")])
+   (set_attr "mode" "V2DF")])

 (define_insn "avx512f_cvtdq2pd512_2"
   [(set (match_operand:V8DF 0 "register_operand" "=v")


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