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[PATCH AArch64 3/3] Fix XOR_one_cmpl pattern; add SIMD-reg variants for BIC,ORN,EON


[When I wrote that xor was broken on GPRs and this fixes it, I meant xor_one_cmpl rather than xor, sorry!]

The pattern for xor_one_cmpl never matched, due to the action of combine_simplify_rtx; hence, separate this pattern out from that for ORN/BIC.

ORN/BIC have equivalent SIMD-reg variants, so add those for the benefit of values in vector registers (e.g. passed as [u]int64x1_t parameters).

EON does not have a SIMD-reg variant; however, it seems better to split it (to XOR + NOT) than to move both arguments to GPRs, perform EON, and move the result back.

gcc/ChangeLog:

	* config/aarch64/aarch64.c (<LOGICAL:optab>_one_cmpl<mode>3):
	Reparameterize to...
	(<NLOGICAL:optab>_one_cmpl<mode>3): with extra SIMD-register variant.
	(xor_one_cmpl<mode>3): New define_insn_and_split.

	* config/aarch64/iterators.md (NLOGICAL): New define_code_iterator.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/eon_1.c: New test.


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