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[PATCH AArch64 1/3] Don't disparage add/sub in SIMD registers
- From: Alan Lawrence <alan dot lawrence at arm dot com>
- To: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Date: Tue, 12 Aug 2014 15:40:39 +0100
- Subject: [PATCH AArch64 1/3] Don't disparage add/sub in SIMD registers
- Authentication-results: sourceware.org; auth=none
- References: <53EA26D1 dot 4010506 at arm dot com>
(It is no more expensive.)
gcc/ChangeLog:
* config/aarch64/aarch64.md (subdi3, adddi3_aarch64): Don't penalize
SIMD reg variant.
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index f8eb305140e7b0aed006b33f1724a90939e48316..0a8ca4bcc7941f912c8d42200b33206d4188fa48 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1188,10 +1188,10 @@
(define_insn "*adddi3_aarch64"
[(set
- (match_operand:DI 0 "register_operand" "=rk,rk,rk,!w")
+ (match_operand:DI 0 "register_operand" "=rk,rk,rk,w")
(plus:DI
- (match_operand:DI 1 "register_operand" "%rk,rk,rk,!w")
- (match_operand:DI 2 "aarch64_plus_operand" "I,r,J,!w")))]
+ (match_operand:DI 1 "register_operand" "%rk,rk,rk,w")
+ (match_operand:DI 2 "aarch64_plus_operand" "I,r,J,w")))]
""
"@
add\\t%x0, %x1, %2
@@ -1662,9 +1662,9 @@
)
(define_insn "subdi3"
- [(set (match_operand:DI 0 "register_operand" "=rk,!w")
- (minus:DI (match_operand:DI 1 "register_operand" "r,!w")
- (match_operand:DI 2 "register_operand" "r,!w")))]
+ [(set (match_operand:DI 0 "register_operand" "=rk,w")
+ (minus:DI (match_operand:DI 1 "register_operand" "r,w")
+ (match_operand:DI 2 "register_operand" "r,w")))]
""
"@
sub\\t%x0, %x1, %x2