This is the mail archive of the mailing list for the GCC project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [PATCH][AArch64] Restrict usage of FP/SIMD registers for TImode reload and absdi2 patterns for non-float/simd targets

On 07/08/14 12:22, Kyrill Tkachov wrote:
> Hi all,
> This patch arises from PR 62014 where apparently gcc generates usage of 
> FP registers with -mgeneral-regs-only. The PR turned out to be bogus in 
> the end that but an inspection of shows that there are some 
> patterns that don't have their usage of FP/SIMD registers properly 
> guarded by the simd attribute or by the TARGET_FLOAT predicate. This 
> patch addresses that, although I could not come up with a testcase that 
> demonstrated wrong behaviour.
> I built the linux kernel with this patch and looked for fmov 
> instructions in the disassembly. They appeared only in the crypto code 
> that uses the new AES instructions and therefore allows usage of vector 
> registers.
> But even without this patch the kernel compiled to an identical binary 
> as with this patch (phew!)
> I've added a comment that hopefully clarifies the usage of the fp and 
> simd attributes.
> Bootstrapped on aarch64-linux and tested on aarch64-none-elf as well.
> Ok for trunk?
> Thanks,
> Kyrill
> 2014-08-07  Kyrylo Tkachov  <>
>      * config/aarch64/ (absdi2): Set simd attribute.
>      (aarch64_reload_mov<mode>): Predicate on TARGET_FLOAT.
>      (aarch64_movdi_<mode>high): Likewise.
>      (aarch64_mov<mode>high_di): Likewise.
>      (aarch64_movdi_<mode>low): Likewise.
>      (aarch64_mov<mode>low_di): Likewise.
>      (aarch64_movtilow_tilow): Likewise.
>      Add comment explaining usage of fp,simd attributes and of



Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]