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[PATCH powerpc64] Add a new constraint to insn movdi_internal64


When compiling an internal application I got an ICE
due to an invalid instruction generated by reload.

Before IRA, I have following insns:

(insn 139 136 581 10 (set (reg:DI 567)
        (const_int 0 [0])) ./strings/stringpiece.h:205 discrim 1 520
     (expr_list:REG_EQUIV (const_int 0 [0])


(insn 231 1062 237 24 (set (reg:V2DI 401 [ vect_cst_.7586 ])
        (vec_concat:V2DI (reg:DI 235 [ fprint$lo_ ])
            (reg:DI 567))) 1066 {vsx_concat_v2di}
     (expr_list:REG_DEAD (reg:DI 235 [ fprint$lo_ ])
        (expr_list:REG_EQUAL (vec_concat:V2DI (reg:DI 235 [ fprint$lo_ ])
                (const_int 0 [0]))

IRA decides register r567 should be spilled into memory

       a48(r567,l0)  -- assign memory
    48:r567 l0   mem

Later when reload pass try to reload the value 0 into VSX register it
calls the hook function rs6000_preferred_reload_class, this function
specifically check the case that reload 0 into a VSX register, then
the target reload register class is VSX register. Then function
gen_reload calls gen_move_insn to generate the reload instruction,
which actually generates a movdi_internal64 insn, and it doesn't
contain a constraint to handle the 0->VSX register case, and causes

VSX instructions can't load a constant into VSX registers directly,
but we can use XOR instruction to generate a 0 value. This patch add a
new constraint to insn pattern movdi_internal64 to load 0 into VSX

Passed regression test without failure. OK for trunk and 4.9 branch?

Guozhi Wei

2014-08-06  Guozhi Wei  <>

        * config/rs6000/ (*movdi_internal64): Add a new constraint.

Attachment: patch
Description: Binary data

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