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Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices at dwf_regno

From: Edmar <edmar at freescale dot com>
To: Ulrich Weigand <uweigand at de dot ibm dot com>
Cc: David Edelsohn <dje dot gcc at gmail dot com>, "rohitarulraj at freescale dot com" <rohitarulraj at freescale dot com>, "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>, Alan Modra <amodra at gmail dot com>, Jakub Jelinek <jakub at redhat dot com>
Date: Mon, 4 Aug 2014 11:51:34 -0500
Subject: Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices at dwf_regno
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References: <201408041025 dot s74APFJK000841 at d06av02 dot portsmouth dot uk dot ibm dot com>

Committed on trunk, revision 213596
Committed on 4.9 branch, revision 213597

I made an omission on the first commit. I did not add
the test case and corresponding ChangeLog entry.
Committed as obvious on trunk, revision 213598

Thanks
Edmar


On 08/04/2014 05:25 AM, Ulrich Weigand wrote:

David Edelsohn wrote:

On Fri, Aug 1, 2014 at 2:03 PM, rohitarulraj@freescale.com
<rohitarulraj@freescale.com>  wrote:

[libgcc]
2014-07-31  Rohit<rohitarulraj@freescale.com>
         * config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Update
           based on change in SPE high register numbers and 3 HTM registers.

[gcc]
2014-07-31  Rohit<rohitarulraj@freescale.com>
         * config/rs6000/rs6000.c
           (rs6000_reg_names) : Add SPE high register names.
           (alt_reg_names) : Likewise.
           (rs6000_dwarf_register_span) : For SPE high registers, replace
           dwarf register numbers with GCC hard register numbers.
           (rs6000_init_dwarf_reg_sizes_extra) : Likewise.
           (rs6000_dbx_register_number): For SPE high registers, return dwarf
           register number for the corresponding GCC hard register number.

         * config/rs6000/rs6000.h
           (FIRST_PSEUDO_REGISTER) : Update based on 32 newly added GCC hard
           register numbers for SPE high registers.
           (DWARF_FRAME_REGISTERS) :  Likewise.
           (DWARF_REG_TO_UNWIND_COLUMN) : Likewise.
           (DWARF_FRAME_REGNUM) : Likewise.
           (FIXED_REGISTERS) : Likewise.
           (CALL_USED_REGISTERS) : Likewise.
           (CALL_REALLY_USED_REGISTERS) : Likewise.
           (REG_ALLOC_ORDER) : Likewise.
           (enum reg_class) : Likewise.
           (REG_CLASS_NAMES) : Likewise.
           (REG_CLASS_CONTENTS) : Likewise.
           (SPE_HIGH_REGNO_P) : New macro to identify SPE high registers.

         * gcc.target/powerpc/pr60102.c: New testcase.

The patch is okay with me if Uli is satisfied.

Yes, this is fine with me.

Bye,
Ulrich

Follow-Ups:
- Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices at dwf_regno
  - From: Jakub Jelinek

References:
- Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices at dwf_regno
  - From: Ulrich Weigand

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