[PATCH][ARM] Enable arm target in ira-shrinkwrap-prep* testcases

[Jiong Wang <jiong dot wang at arm dot com>]

currently the following testcases are disabled for arm target,

gcc.dg/ira-shrinkwrap-prep-1.c
gcc.dg/ira-shrinkwrap-prep-2.c
gcc.dg/pr10474.c
 

the reason is on arm target, register r3 is caller-saved.  Normally it does
not need to be saved on entry by the prologue.  However if we choose to save
it for padding then we may confuse the compiler into thinking a prologue sequence
is required when in fact it is not.  This will occur when shrink-wrapping if r3
is used as a scratch register and there are no other callee-saved writes.

This situation can be avoided when other callee-saved registers are available
and r3 is not mandatory if we choose a callee-saved register for padding.


Dejagnu improvements
===
-UNSUPPORTED: gcc.dg/ira-shrinkwrap-prep-1.c
-UNSUPPORTED: gcc.dg/ira-shrinkwrap-prep-2.c
+PASS: gcc.dg/ira-shrinkwrap-prep-1.c (test for excess errors)
+PASS: gcc.dg/ira-shrinkwrap-prep-1.c scan-rtl-dump ira "Will split live ranges of parameters"
+PASS: gcc.dg/ira-shrinkwrap-prep-1.c scan-rtl-dump ira "Split live-range of register"
+PASS: gcc.dg/ira-shrinkwrap-prep-1.c scan-rtl-dump pro_and_epilogue "Performing shrink-wrapping"
+PASS: gcc.dg/ira-shrinkwrap-prep-2.c (test for excess errors)
+PASS: gcc.dg/ira-shrinkwrap-prep-2.c scan-rtl-dump ira "Will split live ranges of parameters"
+PASS: gcc.dg/ira-shrinkwrap-prep-2.c scan-rtl-dump ira "Split live-range of register"
+PASS: gcc.dg/ira-shrinkwrap-prep-2.c scan-rtl-dump pro_and_epilogue "Performing shrink-wrapping"
-UNSUPPORTED: gcc.dg/pr10474.c
+PASS: gcc.dg/pr10474.c (test for excess errors)
+PASS: gcc.dg/pr10474.c scan-rtl-dump pro_and_epilogue "Performing shrink-wrapping"

ok for trunk ?

thanks.

-- Jiong

gcc/
  * config/arm/arm.c (arm_get_frame_offsets): If both r3 and other callee-saved
    registers are available for padding purpose, and r3 is not mandatory, then
    prefer use those callee-saved instead of r3.

gcc/testsuite/
  * gcc.dg/ira-shrinkwrap-prep-1.c (target): Add arm_nothumb
  * gcc.dg/ira-shrinkwrap-prep-2.c (target): Add arm_nothumb
  * gcc.dg/pr10474.c (target): Add arm_nothumb

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 78cae73..d33c62c 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -20780,30 +20780,47 @@ arm_get_frame_offsets (void)
 	{
 	  int reg = -1;

+	  /* Register r3 is caller-saved.  Normally it does not need to be
+	     saved on entry by the prologue.  However if we choose to save
+	     it for padding then we may confuse the compiler into thinking
+	     a prologue sequence is required when in fact it is not.  This
+	     will occur when shrink-wrapping if r3 is used as a scratch
+	     register and there are no other callee-saved writes.
+
+	     This situation can be avoided when other callee-saved registers
+	     are available and r3 is not mandatory if we choose a callee-saved
+	     register for padding.  */
+	  bool prefer_callee_reg_p = false;
+
 	  /* If it is safe to use r3, then do so.  This sometimes
 	     generates better code on Thumb-2 by avoiding the need to
 	     use 32-bit push/pop instructions.  */
           if (! any_sibcall_could_use_r3 ()
 	      && arm_size_return_regs () <= 12
 	      && (offsets->saved_regs_mask & (1 << 3)) == 0
-              && (TARGET_THUMB2
+	      && (TARGET_THUMB2
 		  || !(TARGET_LDRD && current_tune->prefer_ldrd_strd)))
 	    {
 	      reg = 3;
+	      if (!(TARGET_LDRD && current_tune->prefer_ldrd_strd))
+		prefer_callee_reg_p = true;
+	    }
+	  if (reg == -1
+	      || prefer_callee_reg_p)
+	    {
+	      for (i = 4; i <= (TARGET_THUMB1 ? LAST_LO_REGNUM : 11); i++)
+		{
+		  /* Avoid fixed registers; they may be changed at
+		     arbitrary times so it's unsafe to restore them
+		     during the epilogue.  */
+		  if (!fixed_regs[i]
+		      && (offsets->saved_regs_mask & (1 << i)) == 0)
+		    {
+		      reg = i;
+		      break;
+		    }
+		}
 	    }
-	  else
-	    for (i = 4; i <= (TARGET_THUMB1 ? LAST_LO_REGNUM : 11); i++)
-	      {
-		/* Avoid fixed registers; they may be changed at
-		   arbitrary times so it's unsafe to restore them
-		   during the epilogue.  */
-		if (!fixed_regs[i]
-		    && (offsets->saved_regs_mask & (1 << i)) == 0)
-		  {
-		    reg = i;
-		    break;
-		  }
-	      }

 	  if (reg != -1)
 	    {
diff --git a/gcc/testsuite/gcc.dg/ira-shrinkwrap-prep-1.c b/gcc/testsuite/gcc.dg/ira-shrinkwrap-prep-1.c
index fc7b142..5360844 100644
--- a/gcc/testsuite/gcc.dg/ira-shrinkwrap-prep-1.c
+++ b/gcc/testsuite/gcc.dg/ira-shrinkwrap-prep-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { { x86_64-*-* && lp64 } || { powerpc*-*-* && lp64 } } } } */
+/* { dg-do compile { target { { x86_64-*-* && lp64 } || { { powerpc*-*-* && lp64 } || arm_nothumb } } } } */
 /* { dg-options "-O3 -fdump-rtl-ira -fdump-rtl-pro_and_epilogue -fno-use-caller-save"  } */

 long __attribute__((noinline, noclone))
diff --git a/gcc/testsuite/gcc.dg/ira-shrinkwrap-prep-2.c b/gcc/testsuite/gcc.dg/ira-shrinkwrap-prep-2.c
index 2e5a9cf..d242cac 100644
--- a/gcc/testsuite/gcc.dg/ira-shrinkwrap-prep-2.c
+++ b/gcc/testsuite/gcc.dg/ira-shrinkwrap-prep-2.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { { x86_64-*-* && lp64 } || { powerpc*-*-* && lp64 } } } } */
+/* { dg-do compile { target { { x86_64-*-* && lp64 } || { { powerpc*-*-* && lp64 } || arm_nothumb } } } } */
 /* { dg-options "-O3 -fdump-rtl-ira -fdump-rtl-pro_and_epilogue -fno-use-caller-save"  } */

 long __attribute__((noinline, noclone))
diff --git a/gcc/testsuite/gcc.dg/pr10474.c b/gcc/testsuite/gcc.dg/pr10474.c
index 77ccc46..803fa10 100644
--- a/gcc/testsuite/gcc.dg/pr10474.c
+++ b/gcc/testsuite/gcc.dg/pr10474.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { { x86_64-*-* && lp64 } || { powerpc*-*-* && lp64 } } } } */
+/* { dg-do compile { target { { x86_64-*-* && lp64 } || { { powerpc*-*-* && lp64 } || arm_nothumb } } } } */
 /* { dg-options "-O3 -fdump-rtl-pro_and_epilogue"  } */

 void f(int *i)