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Re: [PATCH] Power/GCC: Implement little-endian SPE operations


On Mon, 7 Jul 2014, David Edelsohn wrote:

> gcc/
> * config/rs6000/rs6000.c (output_vec_const_move): Handle
> little-endian code generation.
> * config/rs6000/spe.md (spe_evmergehi): Rename to...
> (vec_perm00_v2si): ... this.  Handle little-endian code
> generation.
> (spe_evmergehilo): Rename to...
> (vec_perm01_v2si): ... this.  Handle little-endian code
> generation.
> (spe_evmergelo): Rename to...
> (vec_perm11_v2si): ... this.  Handle little-endian code
> generation.
> (spe_evmergelohi): Rename to...
> (vec_perm10_v2si): ... this.  Handle little-endian code
> generation.
> (spe_evmergehi, spe_evmergehilo): New expanders.
> (spe_evmergelo, spe_evmergelohi): Likewise.
> (*frob_<SPE64:mode>_<DITI:mode>): Handle little-endian code
> generation.
> (*frob_tf_ti): Likewise.
> (*frob_<mode>_di_2): Likewise.
> (*frob_tf_di_8_2): Likewise.
> (*frob_di_<mode>): Likewise.
> (*frob_ti_tf): Likewise.
> (*frob_<DITI:mode>_<SPE64:mode>_2): Likewise.
> (*frob_ti_<mode>_8_2): Likewise.
> (*frob_ti_tf_2): Likewise.
> (mov_si<mode>_e500_subreg0): Rename to...
> (mov_si<mode>_e500_subreg0_be): ... this.  Restrict to the big
> endianness only.
> (*mov_si<mode>_e500_subreg0_le): New instruction pattern.
> (*mov_si<mode>_e500_subreg0_elf_low): Rename to...
> (*mov_si<mode>_e500_subreg0_elf_low_be): ... this.  Restrict to
> the big endianness only.
> (*mov_si<mode>_e500_subreg0_elf_low_le): New instruction pattern.
> (*mov_si<mode>_e500_subreg0_2): Rename to...
> (*mov_si<mode>_e500_subreg0_2_be): ... this.  Restrict to the
> big big endianness only.
> (*mov_si<mode>_e500_subreg0_2_le): New instruction pattern.
> (*mov_si<mode>_e500_subreg4): Rename to...
> (*mov_si<mode>_e500_subreg4_be): ... this.  Restrict to the big
> endianness only.
> (mov_si<mode>_e500_subreg4_le): New instruction pattern.
> (*mov_si<mode>_e500_subreg4_elf_low): Rename to...
> (*mov_si<mode>_e500_subreg4_elf_low_be): ... this.  Restrict to
> the big endianness only.
> (*mov_si<mode>_e500_subreg4_elf_low_le): New instruction/splitter
> pattern.
> (*mov_si<mode>_e500_subreg4_2): Rename to...
> (*mov_si<mode>_e500_subreg4_2_be): ... this.  Restrict to the big
> endianness only.
> (*mov_si<mode>_e500_subreg4_2_le): New instruction pattern.
> (*mov_sitf_e500_subreg8): Rename to...
> (*mov_sitf_e500_subreg8_be): ... this.  Restrict to the big
> endianness only.
> (*mov_sitf_e500_subreg8_le): New instruction pattern.
> (*mov_sitf_e500_subreg8_2): Rename to...
> (*mov_sitf_e500_subreg8_2_be): ... this.  Restrict to the big
> endianness only.
> (*mov_sitf_e500_subreg8_2_le): New instruction pattern.
> (*mov_sitf_e500_subreg12): Rename to...
> (*mov_sitf_e500_subreg12_be): ... this.  Restrict to the big
> endianness only.
> (*mov_sitf_e500_subreg12_le): New instruction pattern.
> (*mov_sitf_e500_subreg12_2): Rename to...
> (*mov_sitf_e500_subreg12_2_be): ... this.  Restrict to the big
> endianness only.
> (*mov_sitf_e500_subreg12_2_le): New instruction pattern.
> 
> gcc/testsuite/
> * gcc.target/powerpc/spe-evmerge.c: New file.
> 
> Okay.
> 
> Could you add a short comment explaining what the "0" and "1" labels
> in vec_perm[01][01]_v2si mean?

 Like this?

  Maciej

gcc-ppc-spe-le-update.diff
Index: gcc-fsf-trunk-quilt/gcc/config/rs6000/spe.md
===================================================================
--- gcc-fsf-trunk-quilt.orig/gcc/config/rs6000/spe.md	2014-07-07 15:27:54.258937029 +0100
+++ gcc-fsf-trunk-quilt/gcc/config/rs6000/spe.md	2014-07-07 15:26:43.748937008 +0100
@@ -438,6 +438,11 @@
   [(set_attr "type" "vecload")
    (set_attr  "length" "4")])
 
+;; Integer vector permutation instructions.  The pairs of digits in the
+;; names of these instructions indicate the indices, in the memory vector
+;; element ordering, of the vector elements permuted to the output vector
+;; from the first and the second input vector respectively.
+
 (define_insn "vec_perm00_v2si"
   [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
 	(vec_select:V2SI
@@ -571,6 +576,8 @@
   DONE;
 })
 
+;; End of integer vector permutation instructions.
+
 (define_insn "spe_evnand"
   [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
         (not:V2SI (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")


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