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Re: [PATCH, alpha]: Wrap {un,}aligned_store sequence with memory blockages.


On 07/07/2014 02:10 AM, Richard Biener wrote:
> On Mon, Jun 30, 2014 at 5:54 PM, Richard Henderson <rth@redhat.com> wrote:
>> On 06/29/2014 11:14 AM, Uros Bizjak wrote:
>>>    if (MEM_READONLY_P (x))
>>> +    if (GET_CODE (mem_addr) == AND)
>>> +      return 1;
>>>      return 0;
>>
>> Certainly missing braces here.  But with that fixed the patch looks plausible.
>>  I'll look at it closer later today.
> 
> Umm... but certainly a very gross hack for a special target in a very
> general routine.
> 
> So - please no!
> 
> If addresses with AND are supposed to be barriers then you should
> model this explicitely in the IL and not make it work "magically".

Huh?  We've supported AND as a conflict-with-most address for like forever.
It's not just Alpha that uses them either; at least Altivec as well.

> Maybe use ALIAS_SET_MEMORY_BARRIER instead?


r~


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