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Re: [PATCH, alpha]: Wrap {un,}aligned_store sequence with memory blockages.

On Fri, Jun 27, 2014 at 10:04 PM, Richard Henderson <> wrote:
> On 06/27/2014 10:04 AM, Uros Bizjak wrote:
>> This happened due to the way stores to QImode and HImode locations are
>> implemented on non-BWX targets. The sequence reads full word, does its
>> magic to the part and stores the full word with changed part back to
>> the memory. However - the scheduler mixed two sequences, violating the
>> atomicity of RMW sequence.
> Except that addresses with AND in them (ldq_u, stq_u) are already supposed to
> be memory barriers.  So you shouldn't need to add such to them again.
> I think something else has gone wrong somewhere.

There is am early shortcut for MEM_READOLNY_P in true_dependence_1.

In this case,

(insn 15 13 18 2 (set (reg/f:DI 78 [ b ])
        (mem/u/f/c:DI (reg/f:DI 79) [2 b+0 S8 A64])) rmw.c:7 226 {*movdi}
     (expr_list:REG_DEAD (reg/f:DI 79)

is free to be scheduled before

(insn 13 12 15 2 (set (mem:DI (and:DI (plus:DI (reg/f:DI 72 [ a ])
                    (const_int 1 [0x1]))
                (const_int -8 [0xfffffffffffffff8])) [0  S8 A64])
        (reg:DI 77)) rmw.c:6 226 {*movdi}
     (expr_list:REG_DEAD (reg:DI 77)
        (expr_list:REG_DEAD (reg/f:DI 72 [ a ])

Attached RFC patch also fixes the testcase, trivially preventing
scheduling of (insn 13) before (insn 15).


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