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Re: [AArch64] Implement ADD in vector registers for 32-bit scalar values.
- From: Marcus Shawcroft <marcus dot shawcroft at gmail dot com>
- To: James Greenhalgh <james dot greenhalgh at arm dot com>
- Cc: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Date: Mon, 23 Jun 2014 09:17:22 +0100
- Subject: Re: [AArch64] Implement ADD in vector registers for 32-bit scalar values.
- Authentication-results: sourceware.org; auth=none
- References: <1395997970-27335-1-git-send-email-james dot greenhalgh at arm dot com> <CBECD840-2CDE-4DFE-B917-5B46B7897A99 at gmail dot com> <20140328144805 dot GA31228 at arm dot com> <8DFDE2CC-2D95-43D1-868A-DA941229D1CD at gmail dot com> <20140328153953 dot GA19721 at arm dot com> <20140516103038 dot GA21818 at arm dot com> <20140619131222 dot GB10969 at arm dot com>
On 19 June 2014 14:12, James Greenhalgh <james.greenhalgh@arm.com> wrote:
> This has been sitting waiting for comment for a while now. If we do need a
> mechanism to describe individual costs for alternatives, it will need
> applied to all the existing uses in aarch64.md/aarch64-simd.md. I think
> solving that problem (if we need to) is a seperate patch, and shouldn't
> prevent this one from going in.
Agreed. OK /Marcus