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[PATCH 4/6] rs6000: Merge rotlsi3 and rotldi3


This uses the rotl* extended mnemonics instead of the rlw*nm and rld*cl
mnemonics, because they are shorter and more importantly they look the
same for 32-bit and 64-bit.

Bootstrapped and tested on powerpc64-linux, {-m64,-m64/-mtune=power8,
-m32,-m32/-mpowerpc64}, no regressions.  Okay to apply?


Segher


gcc/
	* config/rs6000/rs6000.md (rotlsi3, *rotlsi3_internal2 and split,
	*rotlsi3_internal3 and split, rotldi3, *rotldi3_internal2 and split,
	*rotldi3_internal3 and split): Delete, merge into...
	(rotl<mode>3, rotl<mode>3_dot, rotl<mode>3_dot2): New.
	(*rotlsi3_64): Fix formatting.  Fix condition.  Replace "i" by "n".
	Use "rotlw" extended mnemonic.

---
 gcc/config/rs6000/rs6000.md | 175 ++++++++++++--------------------------------
 1 file changed, 45 insertions(+), 130 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 77c2161..665fced 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -3853,92 +3853,82 @@ (define_insn "*extzvdi_internal2"
   [(set_attr "type" "shift")
    (set_attr "dot" "yes")])
 
-(define_insn "rotlsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		   (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
+
+(define_insn "rotl<mode>3"
+  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+	(rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
+		    (match_operand:GPR 2 "reg_or_cint_operand" "r,n")))]
   ""
   "@
-   rlwnm %0,%1,%2,0xffffffff
-   rlwinm %0,%1,%h2,0xffffffff"
+   rotl<wd> %0,%1,%2
+   rotl<wd>i %0,%1,%<hH>2"
   [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotlsi3_64"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-  	(zero_extend:DI
+	(zero_extend:DI
 	    (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		       (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
-  "TARGET_64BIT"
+		       (match_operand:SI 2 "reg_or_cint_operand" "r,n"))))]
+  "TARGET_POWERPC64"
   "@
-   rlwnm %0,%1,%2,0xffffffff
-   rlwinm %0,%1,%h2,0xffffffff"
+   rotlw %0,%1,%2
+   rotlwi %0,%1,%h2"
   [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no")])
 
-(define_insn "*rotlsi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			       (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
+(define_insn_and_split "*rotl<mode>3_dot"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
+	(compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")
+				(match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n"))
 		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r,r,r"))]
-  ""
+   (clobber (match_scratch:GPR 0 "=r,r,r,r"))]
+  "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
   "@
-   rlwnm. %3,%1,%2,0xffffffff
-   rlwinm. %3,%1,%h2,0xffffffff
+   rotl<wd>. %0,%1,%2
+   rotl<wd>i. %0,%1,%<hH>2
    #
    #"
+  "&& reload_completed"
+  [(set (match_dup 0)
+	(rotate:GPR (match_dup 1)
+		    (match_dup 2)))
+   (set (match_dup 3)
+	(compare:CC (match_dup 0)
+		    (const_int 0)))]
+  ""
   [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no,yes,no")
    (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
-	(compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			       (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(rotate:SI (match_dup 1) (match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*rotlsi3_internal3"
+(define_insn_and_split "*rotl<mode>3_dot2"
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			       (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
+	(compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")
+				(match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(rotate:SI (match_dup 1) (match_dup 2)))]
-  ""
+   (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r")
+	(rotate:GPR (match_dup 1)
+		    (match_dup 2)))]
+  "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
   "@
-   rlwnm. %0,%1,%2,0xffffffff
-   rlwinm. %0,%1,%h2,0xffffffff
+   rotl<wd>. %0,%1,%2
+   rotl<wd>i. %0,%1,%<hH>2
    #
    #"
+  "&& reload_completed"
+  [(set (match_dup 0)
+	(rotate:GPR (match_dup 1)
+		    (match_dup 2)))
+   (set (match_dup 3)
+	(compare:CC (match_dup 0)
+		    (const_int 0)))]
+  ""
   [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no,yes,no")
    (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
-	(compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			       (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(rotate:SI (match_dup 1) (match_dup 2)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(rotate:SI (match_dup 1) (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
 
 (define_insn "*rotlsi3_internal4"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
@@ -6956,81 +6946,6 @@ (define_expand "umulditi3"
   DONE;
 })
 
-(define_insn "rotldi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-		   (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
-  "TARGET_POWERPC64"
-  "@
-   rldcl %0,%1,%2,0
-   rldicl %0,%1,%H2,0"
-  [(set_attr "type" "shift")
-   (set_attr "var_shift" "yes,no")])
-
-(define_insn "*rotldi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
-			       (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r,r,r"))]
-  "TARGET_64BIT"
-  "@
-   rldcl. %3,%1,%2,0
-   rldicl. %3,%1,%H2,0
-   #
-   #"
-  [(set_attr "type" "shift")
-   (set_attr "var_shift" "yes,no,yes,no")
-   (set_attr "dot" "yes")
-   (set_attr "length" "4,4,8,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
-	(compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			       (match_operand:DI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 3)
-	(rotate:DI (match_dup 1) (match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*rotldi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
-			       (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
-	(rotate:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_64BIT"
-  "@
-   rldcl. %0,%1,%2,0
-   rldicl. %0,%1,%H2,0
-   #
-   #"
-  [(set_attr "type" "shift")
-   (set_attr "var_shift" "yes,no,yes,no")
-   (set_attr "dot" "yes")
-   (set_attr "length" "4,4,8,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
-	(compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			       (match_operand:DI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(rotate:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(rotate:DI (match_dup 1) (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
 (define_insn "*rotldi3_internal4"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
 	(and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-- 
1.8.1.4


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