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Re: Patch improving spilling general regs into vector regs


This patches causes a failure to build GCC (since commit 211655), on
all ARM and Aarch64 targets I track.

I can see failures when building libgcc (_mulsc3.o, _muldc3.o,
_divdc3.o), the error message being:
0xa07f6f crash_signal
Please submit a full bug report,


On 13 June 2014 22:33, Vladimir Makarov <> wrote:
>   Hi, the following patch improves LRA spilling general reg pseduos
> into vector regs.
>   Before the patch only *regular* spilled pseudos of general regs
> class are assigned to vector regs on the LRA spill sub-pass.  The
> patch improves this by assigning vector regs to *inheritance* pseudos
> on LRA assign sub-pass (it should be done here as if an inheritance
> pseudo does not get a hard reg on the sub-pass, it is removed right
> after the sub-pass).
>   As the result on a big benchmark (about 500K lines of fortran code),
> LRA assigns about 25% more spilled pseudos of general regs class to
> vector regs (6123 vs. 4827) in 64-bit mode and about 85% in 32-bit
> mode (22691 vs 12171).
>   The patch also fixes a bug in spilling pseudos into vector regs
> which might result in LRA cycling.  The fix is in i386.c which wrongly
> returned SSE_REGS class for NO_REGS pseudos.  Pseudos denoting
> secondary memory have such class and they might get vector regs and it
> results in secondary memory transformation again and again.  The fix
> is pretty obvious so I am checking it in without an approval.
>   The patch was bootstrapped and tested on x86-64 with switching on
> spilling general reg pseudos into vector regs.
>   Committed as rev. 211655.
> 2014-06-13  Vladimir Makarov  <>
>         * lra-assign.c (assign_by_spills): Add code to assign vector regs
>         to inheritance pseudos.
>         * config/i386/i386.c (ix86_spill_class): Add check on NO_REGS.

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