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[linaro/gcc-4_9-branch] Merge from gcc-4_9-branch and backports


Hi all,

we have merged the gcc-4_9-branch into linaro/gcc-4_9-branch up to
revision 211054 as r211495.  We have also backported this set of revisions:

r209419 as r211497 : PR rtl-optimization/60663
r209457 as r211496 : TRY_EMPTY_VM_SPACE Change aarch64 ilp32
r209559 as r211498 : [AArch64] vrnd<*>_f64 patch
r209561 as r211505 : Suppress Redundant Flag Setting for Cortex-A15.
r209613 as r211506 : AArch32 Support ORN for DIMode
r209614 as r211507 : Optimise NotDI AND/OR ZeroExtendSI for ARMv7A
r209615 as r211508 : [ARM] Allow any register for DImode values in Thumb2
r209617 as r211509 : [AArch64] Fix possible wrong code generation when
comparing DImode values.
r209618 as r211511 : [AArch64] Add a space to memory asm code between
base register and offset.
r209627 as r211512 : [AArch64] Fix indentation.
r209636 as r211512 : [AArch64] Fix aarch64_initial_elimination_offset
calculation.
r209640 as r211514 : [AArch64] vqneg and vqabs intrinsics implementation.
r209641 as r211515 : [AArch64] Vreinterpret re-implemention.
r209642 as r211515 : [AArch64] 64-bit float vreinterpret implemention
r209643 as r211516 : [AArch64] Define TARGET_FLAGS_REGNUM
r209645 as r211517 : [AArch64] Fix TLS for ILP32.
r209649 as r211518 : Merge longlong.h from glibc tree.
r209659 as r211519 : AArch64 add, sub, mul in TImode
r209701 as r211520 : [ARM] Handle FMA code in rtx costs.
r209702 as r211520 : [ARM] Cortex-A8 rtx cost table
r209703 as r211520 : [ARM][1/3] Add rev field to rtx cost tables
r209704 as r211520 : [AArch64][2/3] Recognise rev16 operations on
SImode and DImode data
r209705 as r211520 : [ARM][3/3] Recognise bitwise operations leading
to SImode rev16
r209706 as r211521 : [AArch64] Add handling of bswap operations in rtx costs
r209710 as r211523 : [ARM] Initialize new tune_params values
r209711 as r211524 : [AArch64] Fully support rotate on logical operations.
r209712 as r211530 : [AARCH64] Use standard patterns for stack protection.
r209713 as r211560 : [AArch64] VDUP Testcases
r209736 as r211573 : [AArch64] Vectorise bswap[16,32,64]
r209742 as r211574 : [AArch64] Reverse TBL indices for big-endian.
r209747 as r211575 : Fix warning in libgfortran configure script
r209749 as r211574 : [AArch64] Enable TBL for big-endian.
r209806 as r211576 : [ARM] Initialise T16-related fields in Cortex-A8
tuning struct.
r209808 as r211577 : [ARM] Enable tail call optimization for long call
r209878 as r211578 : [AArch64] Relax modes_tieable_p and
cannot_change_mode_class
r209880 as r211579 : [AArch64] Improve vst4_lane intrinsics
r209893 as r211580 : Add execution + assembler tests of the AArch64
ZIP Intrinsics.
r209897 as r211581 : Remove PUSH_ARGS_REVERSED from the RTL expander.
r209906 as r211582 : [AArch64/ARM 2/3] Rewrite AArch64 ZIP Intrinsics
using __builtin_shuffle
r209908 as r211582 : Add execution tests of ARM ZIP Intrinsics.
r210615 as r211583 : libitm: Enable aarch64
r211211 as r211584 : [AARCH64]Support full addressing modes for
ldr/str in vectorization scenarios

This will be part of our 2014.06 release.

Thanks,
Yvan


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