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Re: [RFC][AArch64] Define TARGET_SPILL_CLASS
- From: Ramana Radhakrishnan <ramana dot gcc at googlemail dot com>
- To: Kugan <kugan dot vivekanandarajah at linaro dot org>
- Cc: Richard Earnshaw <rearnsha at arm dot com>, "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>, Marcus Shawcroft <Marcus dot Shawcroft at arm dot com>
- Date: Thu, 5 Jun 2014 09:29:34 +0100
- Subject: Re: [RFC][AArch64] Define TARGET_SPILL_CLASS
- Authentication-results: sourceware.org; auth=none
- References: <537D3A51 dot 2090006 at linaro dot org> <537DEAFB dot 9030100 at arm dot com> <53857FA4 dot 70405 at linaro dot org>
- Reply-to: ramrad01 at arm dot com
>
> Thanks Richard for the comments. My primary intention here is to use
> TARGET_SPILL_CLASS to make FP_REGS as spill registers.
> Do you think
> AArch64 can benefit from TARGET_SPILL_CLASS hook. I agree that just
> increasing GP2FP and FP2GP for all the modes as I am doing is not the
> right think to do.
>
I suspect TARGET_SPILL_CLASS again needs to be a per-core decision,
the cost of moving between FP and Integer registers really depends on
the implementation and having this spill all the time to FP register
may not be good enough. So a default definition of TARGET_SPILL_CLASS
doesn't sound to me prima-facie.
I don't think increasing GP2FP and FP2GP costs is a bad thing. In a
number of benchmarks we've seen increased moves between FP and integer
registers and having this fix appears to help some of them. However
moving this to generic model needs more benchmarking across a variety
of cores before it can safely be applied there.
regards
Ramana
> Thanks,
> Kugan