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RE: [PATCH][MIPS] Implement O32 FPXX ABI (GCC)
- From: Matthew Fortune <Matthew dot Fortune at imgtec dot com>
- To: Richard Sandiford <rdsandiford at googlemail dot com>
- Cc: "Joseph Myers (joseph at codesourcery dot com)" <joseph at codesourcery dot com>, "macro at codesourcery dot com" <macro at codesourcery dot com>, "Moore, Catherine (Catherine_Moore at mentor dot com)" <Catherine_Moore at mentor dot com>, Rich Fuhler <Rich dot Fuhler at imgtec dot com>, "'gcc-patches at gcc dot gnu dot org' (gcc-patches at gcc dot gnu dot org)" <gcc-patches at gcc dot gnu dot org>
- Date: Mon, 2 Jun 2014 07:53:32 +0000
- Subject: RE: [PATCH][MIPS] Implement O32 FPXX ABI (GCC)
- Authentication-results: sourceware.org; auth=none
- References: <6D39441BF12EF246A7ABCE6654B023535233AE at LEMAIL01 dot le dot imgtec dot org> <87r43qlshb dot fsf at talisman dot default> <6D39441BF12EF246A7ABCE6654B02353539412 at LEMAIL01 dot le dot imgtec dot org> <87ha4ihjhk dot fsf at talisman dot default>
Hi Richard,
I've realised that I may need to do 'something' to prevent GCC from loading or
storing DFmode/DImode values to/from FPRs using pairs of SWC1/LWC1 when using
an unaligned address. Initial tests show that when loading from an unaligned
address (4-byte aligned) then GCC loads the two halves of a 64-bit value into
GPRs and then moves across to FPRs. This is good but I don't know if it is
guaranteed.
From what I can tell the backend doesn't specifically deal with loading
unaligned data but rather the normal load/store patterns are used by the
middle end. As such I'm not sure there is anything to prevent direct loads
to FPRs by parts.
Do you know one way or the other if unaligned doubles can currently be loaded
via pairs of lwc1 (same for store) and if so can you advise on an approach I
could try to prevent this for FPXX? I will try to figure this out on my own in
the meantime.
Regards,
Matthew