diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 74645ee..cae56ae 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -254,29 +254,30 @@ struct tune_params bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool); const struct cpu_cost_table *insn_extra_cost; bool (*sched_adjust_cost) (rtx, rtx, rtx, int *); + int (*branch_cost) (bool, bool); + /* Vectorizer costs. */ + const struct cpu_vec_costs* vec_costs; int constant_limit; /* Maximum number of instructions to conditionalise. */ int max_insns_skipped; int num_prefetch_slots; int l1_cache_size; int l1_cache_line_size; - bool prefer_constant_pool; - int (*branch_cost) (bool, bool); + + enum {PREFER_CONST_POOL_FALSE, PREFER_CONST_POOL_TRUE} + prefer_constant_pool: 1; /* Prefer STRD/LDRD instructions over PUSH/POP/LDM/STM. */ - bool prefer_ldrd_strd; + enum {PREFER_LDRD_FALSE, PREFER_LDRD_TRUE} prefer_ldrd_strd: 1; /* The preference for non short cirtcuit operation when optimizing for performance. The first element covers Thumb state and the second one is for ARM state. */ - bool logical_op_non_short_circuit[2]; - /* Vectorizer costs. */ - const struct cpu_vec_costs* vec_costs; - /* Prefer Neon for 64-bit bitops. */ - bool prefer_neon_for_64bits; + enum log_op_non_sc {LOG_OP_NON_SC_NEVER, LOG_OP_NON_SC_ARM, + LOG_OP_NON_SC_THUMB, LOG_OP_NON_SC_ALL}; + log_op_non_sc logical_op_non_short_circuit: 2; + enum {PREFER_NEON_64_FALSE, PREFER_NEON_64_TRUE} prefer_neon_for_64bits: 1; /* Prefer 32-bit encoding instead of flag-setting 16-bit encoding. */ - bool disparage_flag_setting_t16_encodings; - /* Prefer 32-bit encoding instead of 16-bit encoding where subset of flags - would be set. */ - bool disparage_partial_flag_setting_t16_encodings; + enum {DISPARAGE_FLAGS_NEITHER, DISPARAGE_FLAGS_PARTIAL, DISPARAGE_FLAGS_ALL} + disparage_flag_setting_t16_encodings: 2; }; extern const struct tune_params *current_tune; diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index ccad548..73e7c9c 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1580,16 +1580,16 @@ const struct tune_params arm_slowmul_tune = arm_slowmul_rtx_costs, NULL, NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, /* Vectorizer costs. */ 3, /* Constant limit. */ 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, - true, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false /* Prefer 32-bit encodings. */ + tune_params::PREFER_CONST_POOL_TRUE, + tune_params::PREFER_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_ALL, + tune_params::PREFER_NEON_64_FALSE, + tune_params::DISPARAGE_FLAGS_NEITHER }; const struct tune_params arm_fastmul_tune = @@ -1597,16 +1597,16 @@ const struct tune_params arm_fastmul_tune = arm_fastmul_rtx_costs, NULL, NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, /* Vectorizer costs. */ 1, /* Constant limit. */ 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, - true, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false /* Prefer 32-bit encodings. */ + tune_params::PREFER_CONST_POOL_TRUE, + tune_params::PREFER_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_ALL, + tune_params::PREFER_NEON_64_FALSE, + tune_params::DISPARAGE_FLAGS_NEITHER }; /* StrongARM has early execution of branches, so a sequence that is worth @@ -1617,16 +1617,16 @@ const struct tune_params arm_strongarm_tune = arm_fastmul_rtx_costs, NULL, NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, /* Vectorizer costs. */ 1, /* Constant limit. */ 3, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, - true, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false /* Prefer 32-bit encodings. */ + tune_params::PREFER_CONST_POOL_TRUE, + tune_params::PREFER_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_ALL, + tune_params::PREFER_NEON_64_FALSE, + tune_params::DISPARAGE_FLAGS_NEITHER }; const struct tune_params arm_xscale_tune = @@ -1634,16 +1634,16 @@ const struct tune_params arm_xscale_tune = arm_xscale_rtx_costs, NULL, xscale_sched_adjust_cost, + arm_default_branch_cost, + &arm_default_vec_cost, /* Vectorizer costs. */ 2, /* Constant limit. */ 3, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, - true, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false /* Prefer 32-bit encodings. */ + tune_params::PREFER_CONST_POOL_TRUE, + tune_params::PREFER_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_ALL, + tune_params::PREFER_NEON_64_FALSE, + tune_params::DISPARAGE_FLAGS_NEITHER }; const struct tune_params arm_9e_tune = @@ -1651,16 +1651,16 @@ const struct tune_params arm_9e_tune = arm_9e_rtx_costs, NULL, NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, /* Vectorizer costs. */ 1, /* Constant limit. */ 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, - true, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false /* Prefer 32-bit encodings. */ + tune_params::PREFER_CONST_POOL_TRUE, + tune_params::PREFER_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_ALL, + tune_params::PREFER_NEON_64_FALSE, + tune_params::DISPARAGE_FLAGS_NEITHER }; const struct tune_params arm_v6t2_tune = @@ -1668,16 +1668,16 @@ const struct tune_params arm_v6t2_tune = arm_9e_rtx_costs, NULL, NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, /* Vectorizer costs. */ 1, /* Constant limit. */ 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, - false, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false /* Prefer 32-bit encodings. */ + tune_params::PREFER_CONST_POOL_FALSE, + tune_params::PREFER_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_ALL, + tune_params::PREFER_NEON_64_FALSE, + tune_params::DISPARAGE_FLAGS_NEITHER }; /* Generic Cortex tuning. Use more specific tunings if appropriate. */ @@ -1686,16 +1686,16 @@ const struct tune_params arm_cortex_tune = arm_9e_rtx_costs, &generic_extra_costs, NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, /* Vectorizer costs. */ 1, /* Constant limit. */ 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, - false, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false /* Prefer 32-bit encodings. */ + tune_params::PREFER_CONST_POOL_FALSE, + tune_params::PREFER_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_ALL, + tune_params::PREFER_NEON_64_FALSE, + tune_params::DISPARAGE_FLAGS_NEITHER }; const struct tune_params arm_cortex_a8_tune = @@ -1703,16 +1703,16 @@ const struct tune_params arm_cortex_a8_tune = arm_9e_rtx_costs, &cortexa8_extra_costs, NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, /* Vectorizer costs. */ 1, /* Constant limit. */ 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, - false, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false /* Prefer 32-bit encodings. */ + tune_params::PREFER_CONST_POOL_FALSE, + tune_params::PREFER_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_ALL, + tune_params::PREFER_NEON_64_FALSE, + tune_params::DISPARAGE_FLAGS_NEITHER }; const struct tune_params arm_cortex_a7_tune = @@ -1720,16 +1720,16 @@ const struct tune_params arm_cortex_a7_tune = arm_9e_rtx_costs, &cortexa7_extra_costs, NULL, + arm_default_branch_cost, + &arm_default_vec_cost, /* Vectorizer costs. */ 1, /* Constant limit. */ 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, - false, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false /* Prefer 32-bit encodings. */ + tune_params::PREFER_CONST_POOL_FALSE, + tune_params::PREFER_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_ALL, + tune_params::PREFER_NEON_64_FALSE, + tune_params::DISPARAGE_FLAGS_NEITHER }; const struct tune_params arm_cortex_a15_tune = @@ -1737,50 +1737,50 @@ const struct tune_params arm_cortex_a15_tune = arm_9e_rtx_costs, &cortexa15_extra_costs, NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, /* Vectorizer costs. */ 1, /* Constant limit. */ 2, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, - false, /* Prefer constant pool. */ - arm_default_branch_cost, - true, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - true, true /* Prefer 32-bit encodings. */ + tune_params::PREFER_CONST_POOL_FALSE, + tune_params::PREFER_LDRD_TRUE, + tune_params::LOG_OP_NON_SC_ALL, + tune_params::PREFER_NEON_64_FALSE, + tune_params::DISPARAGE_FLAGS_ALL }; const struct tune_params arm_cortex_a53_tune = { arm_9e_rtx_costs, &cortexa53_extra_costs, - NULL, /* Scheduler cost adjustment. */ + NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, /* Vectorizer costs. */ 1, /* Constant limit. */ 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, - false, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false /* Prefer 32-bit encodings. */ + tune_params::PREFER_CONST_POOL_FALSE, + tune_params::PREFER_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_ALL, + tune_params::PREFER_NEON_64_FALSE, + tune_params::DISPARAGE_FLAGS_NEITHER }; const struct tune_params arm_cortex_a57_tune = { arm_9e_rtx_costs, &cortexa57_extra_costs, - NULL, /* Scheduler cost adjustment. */ - 1, /* Constant limit. */ - 2, /* Max cond insns. */ - ARM_PREFETCH_NOT_BENEFICIAL, - false, /* Prefer constant pool. */ + NULL, /* Sched adj cost. */ arm_default_branch_cost, - true, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - true, true /* Prefer 32-bit encodings. */ + &arm_default_vec_cost, /* Vectorizer costs. */ + 1, /* Constant limit. */ + 2, /* Max cond insns. */ + ARM_PREFETCH_NOT_BENEFICIAL, + tune_params::PREFER_CONST_POOL_FALSE, + tune_params::PREFER_LDRD_TRUE, + tune_params::LOG_OP_NON_SC_ALL, + tune_params::PREFER_NEON_64_FALSE, + tune_params::DISPARAGE_FLAGS_ALL }; /* Branches can be dual-issued on Cortex-A5, so conditional execution is @@ -1791,16 +1791,16 @@ const struct tune_params arm_cortex_a5_tune = arm_9e_rtx_costs, NULL, NULL, /* Sched adj cost. */ + arm_cortex_a5_branch_cost, + &arm_default_vec_cost, /* Vectorizer costs. */ 1, /* Constant limit. */ 1, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, - false, /* Prefer constant pool. */ - arm_cortex_a5_branch_cost, - false, /* Prefer LDRD/STRD. */ - {false, false}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false /* Prefer 32-bit encodings. */ + tune_params::PREFER_CONST_POOL_FALSE, + tune_params::PREFER_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_NEVER, + tune_params::PREFER_NEON_64_FALSE, + tune_params::DISPARAGE_FLAGS_NEITHER }; const struct tune_params arm_cortex_a9_tune = @@ -1808,16 +1808,16 @@ const struct tune_params arm_cortex_a9_tune = arm_9e_rtx_costs, &cortexa9_extra_costs, cortex_a9_sched_adjust_cost, + arm_default_branch_cost, + &arm_default_vec_cost, /* Vectorizer costs. */ 1, /* Constant limit. */ 5, /* Max cond insns. */ ARM_PREFETCH_BENEFICIAL(4,32,32), - false, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false /* Prefer 32-bit encodings. */ + tune_params::PREFER_CONST_POOL_FALSE, + tune_params::PREFER_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_ALL, + tune_params::PREFER_NEON_64_FALSE, + tune_params::DISPARAGE_FLAGS_NEITHER }; const struct tune_params arm_cortex_a12_tune = @@ -1825,16 +1825,16 @@ const struct tune_params arm_cortex_a12_tune = arm_9e_rtx_costs, &cortexa12_extra_costs, NULL, + arm_default_branch_cost, + &arm_default_vec_cost, /* Vectorizer costs. */ 1, /* Constant limit. */ 5, /* Max cond insns. */ ARM_PREFETCH_BENEFICIAL(4,32,32), - false, /* Prefer constant pool. */ - arm_default_branch_cost, - true, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false /* Prefer 32-bit encodings. */ + tune_params::PREFER_CONST_POOL_FALSE, + tune_params::PREFER_LDRD_TRUE, + tune_params::LOG_OP_NON_SC_ALL, + tune_params::PREFER_NEON_64_FALSE, + tune_params::DISPARAGE_FLAGS_NEITHER }; /* armv7m tuning. On Cortex-M4 cores for example, MOVW/MOVT take a single @@ -1849,16 +1849,16 @@ const struct tune_params arm_v7m_tune = arm_9e_rtx_costs, &v7m_extra_costs, NULL, /* Sched adj cost. */ + arm_cortex_m_branch_cost, + &arm_default_vec_cost, /* Vectorizer costs. */ 1, /* Constant limit. */ 2, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, - true, /* Prefer constant pool. */ - arm_cortex_m_branch_cost, - false, /* Prefer LDRD/STRD. */ - {false, false}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false /* Prefer 32-bit encodings. */ + tune_params::PREFER_CONST_POOL_TRUE, + tune_params::PREFER_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_NEVER, + tune_params::PREFER_NEON_64_FALSE, + tune_params::DISPARAGE_FLAGS_NEITHER }; /* The arm_v6m_tune is duplicated from arm_cortex_tune, rather than @@ -1868,16 +1868,16 @@ const struct tune_params arm_v6m_tune = arm_9e_rtx_costs, NULL, NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, /* Vectorizer costs. */ 1, /* Constant limit. */ 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, - false, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {false, false}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false /* Prefer 32-bit encodings. */ + tune_params::PREFER_CONST_POOL_FALSE, + tune_params::PREFER_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_NEVER, + tune_params::PREFER_NEON_64_FALSE, + tune_params::DISPARAGE_FLAGS_NEITHER }; const struct tune_params arm_fa726te_tune = @@ -1885,16 +1885,16 @@ const struct tune_params arm_fa726te_tune = arm_9e_rtx_costs, NULL, fa726te_sched_adjust_cost, + arm_default_branch_cost, + &arm_default_vec_cost, /* Vectorizer costs. */ 1, /* Constant limit. */ 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, - true, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false /* Prefer 32-bit encodings. */ + tune_params::PREFER_CONST_POOL_TRUE, + tune_params::PREFER_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_ALL, + tune_params::PREFER_NEON_64_FALSE, + tune_params::DISPARAGE_FLAGS_NEITHER }; @@ -17010,14 +17010,16 @@ thumb2_reorg (void) FOR_EACH_BB_FN (bb, cfun) { - if (current_tune->disparage_flag_setting_t16_encodings + if ((current_tune->disparage_flag_setting_t16_encodings + == tune_params::DISPARAGE_FLAGS_ALL) && optimize_bb_for_speed_p (bb)) continue; rtx insn; Convert_Action action = SKIP; Convert_Action action_for_partial_flag_setting - = (current_tune->disparage_partial_flag_setting_t16_encodings + = ((current_tune->disparage_flag_setting_t16_encodings + != tune_params::DISPARAGE_FLAGS_NEITHER) && optimize_bb_for_speed_p (bb)) ? SKIP : CONV; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 56da311..f6ab850 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2084,10 +2084,15 @@ enum arm_auto_incmodes (current_tune->branch_cost (speed_p, predictable_p)) /* False if short circuit operation is preferred. */ -#define LOGICAL_OP_NON_SHORT_CIRCUIT \ - ((optimize_size) \ - ? (TARGET_THUMB ? false : true) \ - : (current_tune->logical_op_non_short_circuit[TARGET_ARM])) +#define LOGICAL_OP_NON_SHORT_CIRCUIT \ + ((optimize_size) ? (TARGET_THUMB ? false : true) \ + : (TARGET_THUMB \ + && (current_tune->logical_op_non_short_circuit \ + & tune_params::LOG_OP_NON_SC_THUMB)) ? true \ + : (TARGET_ARM \ + && (current_tune->logical_op_non_short_circuit \ + & tune_params::LOG_OP_NON_SC_ARM)) ? true \ + : false) /* Position Independent Code. */