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Re: [PATCH][ARM] Use mov_imm type for movw operations consistently

On 05/29/14 16:25, Kyrill Tkachov wrote:
Hi all,

I noticed that in some of our move patterns the movw instruction is given the mov_reg type rather than the
mov_imm type that all other uses of movw have. This patch fixes that.

Scanning through our pipeline descriptions I see that mov_imm is treated the same way as mov_reg everywhere anyway. In the Cortex-A7 description we do have a bit more complicated logic:

;; ALU instruction with an immediate operand can dual-issue.
(define_insn_reservation "cortex_a7_alu_imm" 2
    (and (eq_attr "tune" "cortexa7")
         (ior (eq_attr "type" "adr,alu_imm,alus_imm,logic_imm,logics_imm,\
              (and (eq_attr "type" "mov_reg,mov_shift,mov_shift_reg")
                   (not (eq_attr "length" "8")))))

In the two patterns that I change the mov_imm has a length of 4 an hence will still use this reservation.
Thus I don't expect codegen to change at all from this patch but for future scheduling jobs this could make a

This is ok. Well spotted.


Tested arm-none-eabi on qemu.

Ok for trunk?


2014-05-29  Kyrylo Tkachov  <>

	* config/arm/ (*thumb2_movhi_insn): Set type of movw
	to mov_imm.
	* config/arm/ (*thumb2_movsi_vfp): Likewise.

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