[PATCH][AARCH64]Support full addressing modes for ldr/str in vectorization scenarios

["bin.cheng" <bin dot cheng at arm dot com>]

Hi,
I was surprised that GCC didn't support addressing modes like
[REG+OFF]/[REG_REG] for instructions ldr/str in vectorization scenarios.
The generated assembly is bad since all address expressions have to be
computed outside of memory reference.  The root cause is because aarch64
effectively rejects reg-indexing (and const-offset) addressing modes in
aarch64_classify_address and miscellaneous simd patterns.

By fixing this issue, performance of fp benchmarks can be obviously
improved.  It can also help vectorized int cases.

The patch passes bootstrap and regression test on aarch64/little-endian.  It
also passes regression test on aarch64/big-endian except for case
"gcc.target/aarch64/vect-mull.c".  I analyzed the failed case and now
believe it reveals a latent bug in vectorizer on aarch64/big-endian.  The
analysis report is posted at
https://gcc.gnu.org/ml/gcc-patches/2014-05/msg00182.html.  

So is it OK?

Thanks,
bin


2014-05-28  Bin Cheng  <bin.cheng@arm.com>

	* config/aarch64/aarch64.c (aarch64_classify_address)
	(aarch64_legitimize_reload_address): Support full addressing modes
	for vector modes.
	* config/aarch64/aarch64.md (mov<mode>, movmisalign<mode>)
	(*aarch64_simd_mov<mode>, *aarch64_simd_mov<mode>): Relax
predicates.