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Re: [RFC][AArch64] Define TARGET_SPILL_CLASS



On 22/05/14 22:18, Richard Earnshaw wrote:
> On 22/05/14 00:44, Kugan wrote:
>> Compiling some applications with -mgeneral-regs-only produces better
>> code (runs faster) compared to not using it. The difference here is that
>> when -mgeneral-regs-only is not used, floating point register are also
>> used in register allocation. Then IRA/LRA has to move them to core
>> registers before performing operations.
>>
>> I experimented with TARGET_SPILL_CLASS (as in attached patch) to make
>> floating point register class as just spill class for integer pseudos.
>> Though this benefits the application which had this issue. Overall
>> performance with speck2k is neutral (some of the benchmarks benefits a
>> lot but others regress). I am looking to see if I can make it perform
>> better overall. Any suggestions welcome.
>>
>> Attached experimental patch passes regression but 168.wupwise and
>> 187.facerec miscompares now. I am looking at fixing this as well.
>>
> 
> While I'll be the first to admit that the generic costs are currently
> little more than estimates, I'm worried about changing them based on the
> results of one benchmark run on a single (unspecified) implementation.
> The generic costs are intended to be a "best blend" of costs across a
> large range of implementations.  Generically tuned code will not
> necessarily be optimial on every processor -- what's more important is
> that it's not severely sub-optimal on any processor.

Thanks Richard for the comments. My primary intention here is to use
TARGET_SPILL_CLASS to make FP_REGS as spill registers. Do you think
AArch64 can benefit from TARGET_SPILL_CLASS hook. I agree that just
increasing GP2FP and FP2GP for all the modes as I am doing is not the
right think to do.

Thanks,
Kugan


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