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[PATCH][MIPS] Implement O32 FPXX ABI (GCC)

Attached is the patch to implement the O32 FPXX ABI described here:

Corresponding binutils and glibc patches are here:

A few comments on the patch:
*) The hook to enable LRA is a temporary measure. This patch is dependent
   on the LRA work from Robert.
*) Dwarf debug for 64-bit values in floating point values for FPXX can't
   be strictly correct for both 32-bit and 64-bit registers but opts to
   describe one 64-bit register as that is what the FPXX ABI is emulating.
   I have not yet checked what exactly happens in GDB when confronted with
   this and 32-bit registers. This also impacts frame information described
   via mips_save_reg and mips_restore_reg. Advice on this would be
*) ISA_HAS_MXHC1 could be defined as true for all three O32 FP ABIs but
   I left out FP32 to maintain historic behaviour. It should be safe to
   Include it though. Thoughts?
*) Because GCC can be built to have mfpxx or mfp64 as the default option
   the ASM_SPEC has to handle these specially such that they are not
   passed in conjunction with -msingle-float. Depending on how all this
   option handling pans out then this may also need to account for
   msoft-float as well. It is an error to have -msoft-float and -mfp64 in
   the assembler.
*) The REGISTER_PREFIX patch is included here as I need it here but can't
   commit it yet even though it is approved.

I am still working through all the testing that this needs but I am fairly
happy with the current state of this patch. I'll report more test status
as I get it.


2014-05-07  Matthew Fortune  <>

	* config.gcc (--with-fp): New option.
	* (HAVE_AS_MODULE): New config define.
	* config/mips/mips-protos.h (mips_hard_regno_caller_save_mode): New
	* config/mips/mips.c (mips_get_arg_info): Ensure V2SFmode is only
	handled specially with TARGET_PAIRED_SINGLE_FLOAT.
	(mips_return_mode_in_fpr_p): Likewise.
	(mips16_call_stub_mode_suffix): Likewise. 
	(mips_return_fpr_pair): O32 FPR pairs are split over even registers.
	(mips16_build_call_stub): Likewise.
	(mips_output_64bit_xfer): Use mthc1 whenever TARGET_HAS_MXHC1.  Add
	specific cases for TARGET_FPXX to move via memory.
	(mips_dwarf_register_span): For TARGET_FPXX pretend that modes larger
	than UNITS_PER_FPREG do not span registers.
	(mips_file_start): Switch to using .module instead of .gnu_attribute.
	No longer support FP ABI 4 (-mips32r2 -mfp64), replace with FP ABI 6.
	Add FP ABI 5 (-mfpxx).
	(mips_save_reg, mips_restore_reg): Do not split saves for TARGET_FPXX.
	(mips_secondary_reload_class): Only reload FP_REGS via GPRS if the
	register has been chosen.
	(mips_hard_regno_caller_save_mode): Implement.
	(mips_option_override): ABI check for TARGET_FLOATXX.
	(mips_conditional_register_usage): Redefine O32 FP64 to match O32 FP32
	callee-saved behaviour.
	(TARGET_LRA_P) TEMPORARY, Define and enable LRA.
	* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): TARGET_FPXX is
	(MIPS_FP32_OPTION_SPEC): New define.
	(OPTION_DEFAULT_SPECS): Pass through --with-fp=* to -mfp*.
	(ASM_SPEC): Pass through mfpxx/mfp64 but not for msingle-float.
	(HAVE_AS_MODULE): Define default.
	* config/mips/ (define_attr enabled): Implement O32 FPXX ABI.
	(move_doubleword_fpr<mode>): Use ISA_HAS_MXHC1 instead of
	* config/mips/mips.opt (mfpxx): New target option.
	* config/mips/mti-elf.h (DRIVER_SELF_SPECS): Infer FP ABI from arch.
	* config/mips/mti-linux.h (DRIVER_SELF_SPECS): Likewise and remove
	fp64 sysroot.
	* config/mips/t-mti-elf: Remove fp64 multilib.
	* config/mips/t-mti-linux: Likewise.
	* Detect .module support.
	* configure: Regenerate.

	* Handle __mips_fpr == 0.
	* New.
	* New.
	* New.
	* New.
	* New.
	* New.
	* New.
	* New.
	* Support -mfpxx.  Support -ffixed-f*.
	* New.
	* New.
	* New.

	* config/mips/mips16.S: Set .module when supported.  Do not build
	stubs for soft-float.  Update O32 FP64 calling convention and use for
	FPXX when possible.  Add FPXX calling convention fallback case.

Attachment: 0001-Add-O32-FPXX-Support.patch
Description: 0001-Add-O32-FPXX-Support.patch

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