This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [PATCH 2/2, x86] Add palignr support for AVX2.


On Tue, Apr 29, 2014 at 07:58:39AM -0700, H.J. Lu wrote:
> On Tue, Apr 29, 2014 at 6:50 AM, Evgeny Stupachenko <evstupac@gmail.com> wrote:
> > The patch adds use of palignr instruction, when we have one operand
> > permutation like:
> > {5 6 7 0 1 2 3 4}:
> >
> > Treating this as {5 6 7 8 9 a b c} on 2 operands, and therefore palignr on 5.
> >
> > Bootstrap and make check passed.
> >
> > Is it ok?
> >
> > Evgeny
> >
> > 2014-04-29  Evgeny Stupachenko  <evstupac@gmail.com>
> >
> >         * config/i386/i386.c (expand_vec_perm_palignr_one_operand): New.
> >         Enables PALIGNR on one operand permutation.
> >         * config/i386/i386.c (expand_vec_perm_1): Try PALIGNR on one operand.
> >
> >
> 
> I think it is better to include some testcases in this
> patch so that the backend change and its testcases
> are self-contained.

Note that most likely it should be already covered by
gcc.dg/torture/vshuf*.c, especially with GCC_TEST_RUN_EXPENSIVE=1.
Though, apparently we need to add new tests for AVX-512, because
v64qi, v32hi, v16si and v8di aren't covered (the last 3 are trivial,
for v64qi supposedly we'd need to write new vshuf-64.inc.

	Jakub


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]