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[AArch64/ARM 1/3] Add execution + assembler tests of AArch64 REV Neon Intrinsics


This adds DejaGNU tests of the existing AArch64 vrev_* intrinsics, both checking the assembler output and the runtime results. Test bodies are in separate files ready to reuse for ARM in the third patch.

All tests passing on aarch64-none-elf and aarch64_be-none-elf.

gcc/testsuite/ChangeLog:

2014-04-23  Alan Lawrence  <alan.lawrence@arm.com>

	* gcc.target/aarch64/simd/vrev16p8_1.c: New file.
	* gcc.target/aarch64/simd/vrev16p8.x: New file.
	* gcc.target/aarch64/simd/vrev16qp8_1.c: New file.
	* gcc.target/aarch64/simd/vrev16qp8.x: New file.
	* gcc.target/aarch64/simd/vrev16qs8_1.c: New file.
	* gcc.target/aarch64/simd/vrev16qs8.x: New file.
	* gcc.target/aarch64/simd/vrev16qu8_1.c: New file.
	* gcc.target/aarch64/simd/vrev16qu8.x: New file.
	* gcc.target/aarch64/simd/vrev16s8_1.c: New file.
	* gcc.target/aarch64/simd/vrev16s8.x: New file.
	* gcc.target/aarch64/simd/vrev16u8_1.c: New file.
	* gcc.target/aarch64/simd/vrev16u8.x: New file.
	* gcc.target/aarch64/simd/vrev32p16_1.c: New file.
	* gcc.target/aarch64/simd/vrev32p16.x: New file.
	* gcc.target/aarch64/simd/vrev32p8_1.c: New file.
	* gcc.target/aarch64/simd/vrev32p8.x: New file.
	* gcc.target/aarch64/simd/vrev32qp16_1.c: New file.
	* gcc.target/aarch64/simd/vrev32qp16.x: New file.
	* gcc.target/aarch64/simd/vrev32qp8_1.c: New file.
	* gcc.target/aarch64/simd/vrev32qp8.x: New file.
	* gcc.target/aarch64/simd/vrev32qs16_1.c: New file.
	* gcc.target/aarch64/simd/vrev32qs16.x: New file.
	* gcc.target/aarch64/simd/vrev32qs8_1.c: New file.
	* gcc.target/aarch64/simd/vrev32qs8.x: New file.
	* gcc.target/aarch64/simd/vrev32qu16_1.c: New file.
	* gcc.target/aarch64/simd/vrev32qu16.x: New file.
	* gcc.target/aarch64/simd/vrev32qu8_1.c: New file.
	* gcc.target/aarch64/simd/vrev32qu8.x: New file.
	* gcc.target/aarch64/simd/vrev32s16_1.c: New file.
	* gcc.target/aarch64/simd/vrev32s16.x: New file.
	* gcc.target/aarch64/simd/vrev32s8_1.c: New file.
	* gcc.target/aarch64/simd/vrev32s8.x: New file.
	* gcc.target/aarch64/simd/vrev32u16_1.c: New file.
	* gcc.target/aarch64/simd/vrev32u16.x: New file.
	* gcc.target/aarch64/simd/vrev32u8_1.c: New file.
	* gcc.target/aarch64/simd/vrev32u8.x: New file.
	* gcc.target/aarch64/simd/vrev64f32_1.c: New file.
	* gcc.target/aarch64/simd/vrev64f32.x: New file.
	* gcc.target/aarch64/simd/vrev64p16_1.c: New file.
	* gcc.target/aarch64/simd/vrev64p16.x: New file.
	* gcc.target/aarch64/simd/vrev64p8_1.c: New file.
	* gcc.target/aarch64/simd/vrev64p8.x: New file.
	* gcc.target/aarch64/simd/vrev64qf32_1.c: New file.
	* gcc.target/aarch64/simd/vrev64qf32.x: New file.
	* gcc.target/aarch64/simd/vrev64qp16_1.c: New file.
	* gcc.target/aarch64/simd/vrev64qp16.x: New file.
	* gcc.target/aarch64/simd/vrev64qp8_1.c: New file.
	* gcc.target/aarch64/simd/vrev64qp8.x: New file.
	* gcc.target/aarch64/simd/vrev64qs16_1.c: New file.
	* gcc.target/aarch64/simd/vrev64qs16.x: New file.
	* gcc.target/aarch64/simd/vrev64qs32_1.c: New file.
	* gcc.target/aarch64/simd/vrev64qs32.x: New file.
	* gcc.target/aarch64/simd/vrev64qs8_1.c: New file.
	* gcc.target/aarch64/simd/vrev64qs8.x: New file.
	* gcc.target/aarch64/simd/vrev64qu16_1.c: New file.
	* gcc.target/aarch64/simd/vrev64qu16.x: New file.
	* gcc.target/aarch64/simd/vrev64qu32_1.c: New file.
	* gcc.target/aarch64/simd/vrev64qu32.x: New file.
	* gcc.target/aarch64/simd/vrev64qu8_1.c: New file.
	* gcc.target/aarch64/simd/vrev64qu8.x: New file.
	* gcc.target/aarch64/simd/vrev64s16_1.c: New file.
	* gcc.target/aarch64/simd/vrev64s16.x: New file.
	* gcc.target/aarch64/simd/vrev64s32_1.c: New file.
	* gcc.target/aarch64/simd/vrev64s32.x: New file.
	* gcc.target/aarch64/simd/vrev64s8_1.c: New file.
	* gcc.target/aarch64/simd/vrev64s8.x: New file.
	* gcc.target/aarch64/simd/vrev64u16_1.c: New file.
	* gcc.target/aarch64/simd/vrev64u16.x: New file.
	* gcc.target/aarch64/simd/vrev64u32_1.c: New file.
	* gcc.target/aarch64/simd/vrev64u32.x: New file.
	* gcc.target/aarch64/simd/vrev64u8_1.c: New file.
	* gcc.target/aarch64/simd/vrev64u8.x: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev16p8.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev16p8.x
new file mode 100644
index 0000000..6316abf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev16p8.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+poly8x8_t
+test_vrev16p8 (poly8x8_t _arg)
+{
+  return vrev16_p8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  poly8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+  poly8x8_t reversed = test_vrev16p8 (inorder);
+  poly8x8_t expected = {2, 1, 4, 3, 6, 5, 8, 7};
+
+  for (i = 0; i < 8; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev16p8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev16p8_1.c
new file mode 100644
index 0000000..da6fc8d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev16p8_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev16_p8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev16p8.x"
+
+/* { dg-final { scan-assembler-times "rev16\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev16qp8.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev16qp8.x
new file mode 100644
index 0000000..318ea7c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev16qp8.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+poly8x16_t
+test_vrev16qp8 (poly8x16_t _arg)
+{
+  return vrev16q_p8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  poly8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+  poly8x16_t reversed = test_vrev16qp8 (inorder);
+  poly8x16_t expected = {2, 1, 4, 3, 6, 5, 8, 7, 10, 9, 12, 11, 14, 13, 16, 15};
+
+  for (i = 0; i < 16; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev16qp8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev16qp8_1.c
new file mode 100644
index 0000000..c553320
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev16qp8_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev16q_p8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev16qp8.x"
+
+/* { dg-final { scan-assembler-times "rev16\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev16qs8.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev16qs8.x
new file mode 100644
index 0000000..a7680f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev16qs8.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int8x16_t
+test_vrev16qs8 (int8x16_t _arg)
+{
+  return vrev16q_s8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+  int8x16_t reversed = test_vrev16qs8 (inorder);
+  int8x16_t expected = {2, 1, 4, 3, 6, 5, 8, 7, 10, 9, 12, 11, 14, 13, 16, 15};
+
+  for (i = 0; i < 16; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev16qs8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev16qs8_1.c
new file mode 100644
index 0000000..9e11c20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev16qs8_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev16q_s8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev16qs8.x"
+
+/* { dg-final { scan-assembler-times "rev16\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev16qu8.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev16qu8.x
new file mode 100644
index 0000000..3550e86
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev16qu8.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint8x16_t
+test_vrev16qu8 (uint8x16_t _arg)
+{
+  return vrev16q_u8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+  uint8x16_t reversed = test_vrev16qu8 (inorder);
+  uint8x16_t expected = {2, 1, 4, 3, 6, 5, 8, 7, 10, 9, 12, 11, 14, 13, 16, 15};
+
+  for (i = 0; i < 16; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev16qu8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev16qu8_1.c
new file mode 100644
index 0000000..33f7fc9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev16qu8_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev16q_u8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev16qu8.x"
+
+/* { dg-final { scan-assembler-times "rev16\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev16s8.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev16s8.x
new file mode 100644
index 0000000..8b5996e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev16s8.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int8x8_t
+test_vrev16s8 (int8x8_t _arg)
+{
+  return vrev16_s8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+  int8x8_t reversed = test_vrev16s8 (inorder);
+  int8x8_t expected = {2, 1, 4, 3, 6, 5, 8, 7};
+
+  for (i = 0; i < 8; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev16s8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev16s8_1.c
new file mode 100644
index 0000000..de64c22
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev16s8_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev16_s8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev16s8.x"
+
+/* { dg-final { scan-assembler-times "rev16\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev16u8.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev16u8.x
new file mode 100644
index 0000000..e5c4912
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev16u8.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint8x8_t
+test_vrev16u8 (uint8x8_t _arg)
+{
+  return vrev16_u8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+  uint8x8_t reversed = test_vrev16u8 (inorder);
+  uint8x8_t expected = {2, 1, 4, 3, 6, 5, 8, 7};
+
+  for (i = 0; i < 8; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev16u8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev16u8_1.c
new file mode 100644
index 0000000..9f117eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev16u8_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev16_u8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev16u8.x"
+
+/* { dg-final { scan-assembler-times "rev16\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32p16.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev32p16.x
new file mode 100644
index 0000000..257b5e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32p16.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+poly16x4_t
+test_vrev32p16 (poly16x4_t _arg)
+{
+  return vrev32_p16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  poly16x4_t inorder = {1, 2, 3, 4};
+  poly16x4_t reversed = test_vrev32p16 (inorder);
+  poly16x4_t expected = {2, 1, 4, 3};
+
+  for (i = 0; i < 4; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32p16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev32p16_1.c
new file mode 100644
index 0000000..6184399
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32p16_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev32_p16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32p16.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.4h, ?v\[0-9\]+.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32p8.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev32p8.x
new file mode 100644
index 0000000..4ccef82
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32p8.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+poly8x8_t
+test_vrev32p8 (poly8x8_t _arg)
+{
+  return vrev32_p8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  poly8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+  poly8x8_t reversed = test_vrev32p8 (inorder);
+  poly8x8_t expected = {4, 3, 2, 1, 8, 7, 6, 5};
+
+  for (i = 0; i < 8; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32p8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev32p8_1.c
new file mode 100644
index 0000000..05fb7f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32p8_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev32_p8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32p8.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32qp16.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qp16.x
new file mode 100644
index 0000000..6640992
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qp16.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+poly16x8_t
+test_vrev32qp16 (poly16x8_t _arg)
+{
+  return vrev32q_p16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  poly16x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+  poly16x8_t reversed = test_vrev32qp16 (inorder);
+  poly16x8_t expected = {2, 1, 4, 3, 6, 5, 8, 7};
+
+  for (i = 0; i < 8; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32qp16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qp16_1.c
new file mode 100644
index 0000000..5903a46
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qp16_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev32q_p16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32qp16.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.8h, ?v\[0-9\]+.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32qp8.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qp8.x
new file mode 100644
index 0000000..4cf6d05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qp8.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+poly8x16_t
+test_vrev32qp8 (poly8x16_t _arg)
+{
+  return vrev32q_p8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  poly8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+  poly8x16_t reversed = test_vrev32qp8 (inorder);
+  poly8x16_t expected = {4, 3, 2, 1, 8, 7, 6, 5, 12, 11, 10, 9, 16, 15, 14, 13};
+
+  for (i = 0; i < 16; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32qp8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qp8_1.c
new file mode 100644
index 0000000..9830a74
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qp8_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev32q_p8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32qp8.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32qs16.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qs16.x
new file mode 100644
index 0000000..b9342cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qs16.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int16x8_t
+test_vrev32qs16 (int16x8_t _arg)
+{
+  return vrev32q_s16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int16x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+  int16x8_t reversed = test_vrev32qs16 (inorder);
+  int16x8_t expected = {2, 1, 4, 3, 6, 5, 8, 7};
+
+  for (i = 0; i < 8; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32qs16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qs16_1.c
new file mode 100644
index 0000000..075e5b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qs16_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev32q_s16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32qs16.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.8h, ?v\[0-9\]+.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32qs8.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qs8.x
new file mode 100644
index 0000000..012ef0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qs8.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int8x16_t
+test_vrev32qs8 (int8x16_t _arg)
+{
+  return vrev32q_s8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+  int8x16_t reversed = test_vrev32qs8 (inorder);
+  int8x16_t expected = {4, 3, 2, 1, 8, 7, 6, 5, 12, 11, 10, 9, 16, 15, 14, 13};
+
+  for (i = 0; i < 16; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32qs8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qs8_1.c
new file mode 100644
index 0000000..03d77d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qs8_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev32q_s8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32qs8.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32qu16.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qu16.x
new file mode 100644
index 0000000..8db7b83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qu16.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint16x8_t
+test_vrev32qu16 (uint16x8_t _arg)
+{
+  return vrev32q_u16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint16x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+  uint16x8_t reversed = test_vrev32qu16 (inorder);
+  uint16x8_t expected = {2, 1, 4, 3, 6, 5, 8, 7};
+
+  for (i = 0; i < 8; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32qu16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qu16_1.c
new file mode 100644
index 0000000..5a02299
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qu16_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev32q_u16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32qu16.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.8h, ?v\[0-9\]+.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32qu8.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qu8.x
new file mode 100644
index 0000000..a241af3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qu8.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint8x16_t
+test_vrev32qu8 (uint8x16_t _arg)
+{
+  return vrev32q_u8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+  uint8x16_t reversed = test_vrev32qu8 (inorder);
+  uint8x16_t expected = {4, 3, 2, 1, 8, 7, 6, 5, 12, 11, 10, 9, 16, 15, 14, 13};
+
+  for (i = 0; i < 16; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32qu8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qu8_1.c
new file mode 100644
index 0000000..d86030d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32qu8_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev32q_u8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32qu8.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32s16.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev32s16.x
new file mode 100644
index 0000000..6cc30cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32s16.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int16x4_t
+test_vrev32s16 (int16x4_t _arg)
+{
+  return vrev32_s16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int16x4_t inorder = {1, 2, 3, 4};
+  int16x4_t reversed = test_vrev32s16 (inorder);
+  int16x4_t expected = {2, 1, 4, 3};
+
+  for (i = 0; i < 4; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32s16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev32s16_1.c
new file mode 100644
index 0000000..badcb73
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32s16_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev32_s16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32s16.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.4h, ?v\[0-9\]+.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32s8.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev32s8.x
new file mode 100644
index 0000000..25b0397
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32s8.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int8x8_t
+test_vrev32s8 (int8x8_t _arg)
+{
+  return vrev32_s8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+  int8x8_t reversed = test_vrev32s8 (inorder);
+  int8x8_t expected = {4, 3, 2, 1, 8, 7, 6, 5};
+
+  for (i = 0; i < 8; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32s8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev32s8_1.c
new file mode 100644
index 0000000..788601e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32s8_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev32_s8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32s8.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32u16.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev32u16.x
new file mode 100644
index 0000000..0e0df08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32u16.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint16x4_t
+test_vrev32u16 (uint16x4_t _arg)
+{
+  return vrev32_u16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint16x4_t inorder = {1, 2, 3, 4};
+  uint16x4_t reversed = test_vrev32u16 (inorder);
+  uint16x4_t expected = {2, 1, 4, 3};
+
+  for (i = 0; i < 4; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32u16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev32u16_1.c
new file mode 100644
index 0000000..ed722c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32u16_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev32_u16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32u16.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.4h, ?v\[0-9\]+.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32u8.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev32u8.x
new file mode 100644
index 0000000..4de3e38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32u8.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint8x8_t
+test_vrev32u8 (uint8x8_t _arg)
+{
+  return vrev32_u8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+  uint8x8_t reversed = test_vrev32u8 (inorder);
+  uint8x8_t expected = {4, 3, 2, 1, 8, 7, 6, 5};
+
+  for (i = 0; i < 8; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev32u8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev32u8_1.c
new file mode 100644
index 0000000..157e04f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev32u8_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev32_u8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32u8.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64f32.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev64f32.x
new file mode 100644
index 0000000..94ec0cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64f32.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+float32x2_t
+test_vrev64f32 (float32x2_t _arg)
+{
+  return vrev64_f32 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  float32x2_t inorder = {1, 2};
+  float32x2_t reversed = test_vrev64f32 (inorder);
+  float32x2_t expected = {2, 1};
+
+  for (i = 0; i < 2; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64f32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev64f32_1.c
new file mode 100644
index 0000000..2d61b34
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64f32_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev64_f32' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64f32.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.2s, ?v\[0-9\]+.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64p16.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev64p16.x
new file mode 100644
index 0000000..43d7032
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64p16.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+poly16x4_t
+test_vrev64p16 (poly16x4_t _arg)
+{
+  return vrev64_p16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  poly16x4_t inorder = {1, 2, 3, 4};
+  poly16x4_t reversed = test_vrev64p16 (inorder);
+  poly16x4_t expected = {4, 3, 2, 1};
+
+  for (i = 0; i < 4; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64p16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev64p16_1.c
new file mode 100644
index 0000000..99a314d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64p16_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev64_p16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64p16.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.4h, ?v\[0-9\]+.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64p8.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev64p8.x
new file mode 100644
index 0000000..6d32ecc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64p8.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+poly8x8_t
+test_vrev64p8 (poly8x8_t _arg)
+{
+  return vrev64_p8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  poly8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+  poly8x8_t reversed = test_vrev64p8 (inorder);
+  poly8x8_t expected = {8, 7, 6, 5, 4, 3, 2, 1};
+
+  for (i = 0; i < 8; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64p8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev64p8_1.c
new file mode 100644
index 0000000..e14465e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64p8_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev64_p8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64p8.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64qf32.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qf32.x
new file mode 100644
index 0000000..79146f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qf32.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+float32x4_t
+test_vrev64qf32 (float32x4_t _arg)
+{
+  return vrev64q_f32 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  float32x4_t inorder = {1, 2, 3, 4};
+  float32x4_t reversed = test_vrev64qf32 (inorder);
+  float32x4_t expected = {2, 1, 4, 3};
+
+  for (i = 0; i < 4; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64qf32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qf32_1.c
new file mode 100644
index 0000000..a8690d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qf32_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev64q_f32' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64qf32.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.4s, ?v\[0-9\]+.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64qp16.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qp16.x
new file mode 100644
index 0000000..5bce38c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qp16.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+poly16x8_t
+test_vrev64qp16 (poly16x8_t _arg)
+{
+  return vrev64q_p16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  poly16x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+  poly16x8_t reversed = test_vrev64qp16 (inorder);
+  poly16x8_t expected = {4, 3, 2, 1, 8, 7, 6, 5};
+
+  for (i = 0; i < 8; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64qp16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qp16_1.c
new file mode 100644
index 0000000..e234ffc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qp16_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev64q_p16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64qp16.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.8h, ?v\[0-9\]+.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64qp8.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qp8.x
new file mode 100644
index 0000000..7e8faca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qp8.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+poly8x16_t
+test_vrev64qp8 (poly8x16_t _arg)
+{
+  return vrev64q_p8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  poly8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+  poly8x16_t reversed = test_vrev64qp8 (inorder);
+  poly8x16_t expected = {8, 7, 6, 5, 4, 3, 2, 1, 16, 15, 14, 13, 12, 11, 10, 9};
+
+  for (i = 0; i < 16; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64qp8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qp8_1.c
new file mode 100644
index 0000000..71a949c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qp8_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev64q_p8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64qp8.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs16.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs16.x
new file mode 100644
index 0000000..9732727
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs16.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int16x8_t
+test_vrev64qs16 (int16x8_t _arg)
+{
+  return vrev64q_s16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int16x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+  int16x8_t reversed = test_vrev64qs16 (inorder);
+  int16x8_t expected = {4, 3, 2, 1, 8, 7, 6, 5};
+
+  for (i = 0; i < 8; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs16_1.c
new file mode 100644
index 0000000..12360b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs16_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev64q_s16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64qs16.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.8h, ?v\[0-9\]+.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs32.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs32.x
new file mode 100644
index 0000000..e35c466
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs32.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int32x4_t
+test_vrev64qs32 (int32x4_t _arg)
+{
+  return vrev64q_s32 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int32x4_t inorder = {1, 2, 3, 4};
+  int32x4_t reversed = test_vrev64qs32 (inorder);
+  int32x4_t expected = {2, 1, 4, 3};
+
+  for (i = 0; i < 4; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs32_1.c
new file mode 100644
index 0000000..8463c5d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs32_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev64q_s32' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64qs32.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.4s, ?v\[0-9\]+.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs8.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs8.x
new file mode 100644
index 0000000..a618918
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs8.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int8x16_t
+test_vrev64qs8 (int8x16_t _arg)
+{
+  return vrev64q_s8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+  int8x16_t reversed = test_vrev64qs8 (inorder);
+  int8x16_t expected = {8, 7, 6, 5, 4, 3, 2, 1, 16, 15, 14, 13, 12, 11, 10, 9};
+
+  for (i = 0; i < 16; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs8_1.c
new file mode 100644
index 0000000..53416aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs8_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev64q_s8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64qs8.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu16.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu16.x
new file mode 100644
index 0000000..db82eb5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu16.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint16x8_t
+test_vrev64qu16 (uint16x8_t _arg)
+{
+  return vrev64q_u16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint16x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+  uint16x8_t reversed = test_vrev64qu16 (inorder);
+  uint16x8_t expected = {4, 3, 2, 1, 8, 7, 6, 5};
+
+  for (i = 0; i < 8; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu16_1.c
new file mode 100644
index 0000000..8641353
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu16_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev64q_u16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64qu16.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.8h, ?v\[0-9\]+.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu32.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu32.x
new file mode 100644
index 0000000..c021493
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu32.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint32x4_t
+test_vrev64qu32 (uint32x4_t _arg)
+{
+  return vrev64q_u32 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint32x4_t inorder = {1, 2, 3, 4};
+  uint32x4_t reversed = test_vrev64qu32 (inorder);
+  uint32x4_t expected = {2, 1, 4, 3};
+
+  for (i = 0; i < 4; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu32_1.c
new file mode 100644
index 0000000..b034780
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu32_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev64q_u32' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64qu32.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.4s, ?v\[0-9\]+.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu8.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu8.x
new file mode 100644
index 0000000..f239ec6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu8.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint8x16_t
+test_vrev64qu8 (uint8x16_t _arg)
+{
+  return vrev64q_u8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+  uint8x16_t reversed = test_vrev64qu8 (inorder);
+  uint8x16_t expected = {8, 7, 6, 5, 4, 3, 2, 1, 16, 15, 14, 13, 12, 11, 10, 9};
+
+  for (i = 0; i < 16; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu8_1.c
new file mode 100644
index 0000000..77e19ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu8_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev64q_u8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64qu8.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64s16.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev64s16.x
new file mode 100644
index 0000000..6593880
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64s16.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int16x4_t
+test_vrev64s16 (int16x4_t _arg)
+{
+  return vrev64_s16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int16x4_t inorder = {1, 2, 3, 4};
+  int16x4_t reversed = test_vrev64s16 (inorder);
+  int16x4_t expected = {4, 3, 2, 1};
+
+  for (i = 0; i < 4; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64s16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev64s16_1.c
new file mode 100644
index 0000000..d2483ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64s16_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev64_s16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64s16.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.4h, ?v\[0-9\]+.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64s32.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev64s32.x
new file mode 100644
index 0000000..25a6bc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64s32.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int32x2_t
+test_vrev64s32 (int32x2_t _arg)
+{
+  return vrev64_s32 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int32x2_t inorder = {1, 2};
+  int32x2_t reversed = test_vrev64s32 (inorder);
+  int32x2_t expected = {2, 1};
+
+  for (i = 0; i < 2; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64s32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev64s32_1.c
new file mode 100644
index 0000000..5254629
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64s32_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev64_s32' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64s32.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.2s, ?v\[0-9\]+.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64s8.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev64s8.x
new file mode 100644
index 0000000..4c23953
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64s8.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int8x8_t
+test_vrev64s8 (int8x8_t _arg)
+{
+  return vrev64_s8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+  int8x8_t reversed = test_vrev64s8 (inorder);
+  int8x8_t expected = {8, 7, 6, 5, 4, 3, 2, 1};
+
+  for (i = 0; i < 8; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64s8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev64s8_1.c
new file mode 100644
index 0000000..96bf1fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64s8_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev64_s8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64s8.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64u16.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev64u16.x
new file mode 100644
index 0000000..49f20d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64u16.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint16x4_t
+test_vrev64u16 (uint16x4_t _arg)
+{
+  return vrev64_u16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint16x4_t inorder = {1, 2, 3, 4};
+  uint16x4_t reversed = test_vrev64u16 (inorder);
+  uint16x4_t expected = {4, 3, 2, 1};
+
+  for (i = 0; i < 4; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64u16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev64u16_1.c
new file mode 100644
index 0000000..7408d76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64u16_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev64_u16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64u16.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.4h, ?v\[0-9\]+.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64u32.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev64u32.x
new file mode 100644
index 0000000..7ec0654
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64u32.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint32x2_t
+test_vrev64u32 (uint32x2_t _arg)
+{
+  return vrev64_u32 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint32x2_t inorder = {1, 2};
+  uint32x2_t reversed = test_vrev64u32 (inorder);
+  uint32x2_t expected = {2, 1};
+
+  for (i = 0; i < 2; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64u32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev64u32_1.c
new file mode 100644
index 0000000..be64c97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64u32_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev64_u32' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64u32.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.2s, ?v\[0-9\]+.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64u8.x b/gcc/testsuite/gcc.target/aarch64/simd/vrev64u8.x
new file mode 100644
index 0000000..dc6dbd1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64u8.x
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint8x8_t
+test_vrev64u8 (uint8x8_t _arg)
+{
+  return vrev64_u8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+  uint8x8_t reversed = test_vrev64u8 (inorder);
+  uint8x8_t expected = {8, 7, 6, 5, 4, 3, 2, 1};
+
+  for (i = 0; i < 8; i++)
+    if (reversed[i] != expected[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrev64u8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrev64u8_1.c
new file mode 100644
index 0000000..ffbc98f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrev64u8_1.c
@@ -0,0 +1,10 @@
+/* Test the `vrev64_u8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64u8.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */

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