Re: [PATCH, ARM] Fix ICE due to out of bound.

[Ramana Radhakrishnan <ramrad01 at arm dot com>]

On 03/19/14 08:42, Zhenqiang Chen wrote:
> Hi,
>
> ICE when compiling gcc.target/arm/neon-modes-3.c with "-g" in
> arm_dwarf_register_span since parts[8] is out of bound for XImode.
> GET_MODE_SIZE (XImode) / 4 is 16. "rtx parts[8]" can not hold all the
> registers.
>
> According to arm-modes.def, 16 should be the biggest number. So the
> patch updates parts to
>
> rtx parts[16];
>
> Bootstrap and no make check regression on ARM Chrome book.
>
> OK for trunk?

It may be time in 4.10 or 5.0 (whatever we call it :)), to deal with the 
FIXME in arm_dwarf_register_span to deal with DW_OP_piece. I'm surprised 
that it's taken so long to hit this.

This is OK for stage4 - it looks sane to me but this needs an RM ack 
before applying.

regards
Ramana

> Thanks!
> -Zhenqiang
>
> ChangeLog:
> 2014-03-19  Zhenqiang Chen  <zhenqiang.chen@linaro.org>
>
>      * config/arm/arm.c (arm_dwarf_register_span): Update the element number
>      of parts.
>
> testsuite/ChangeLog:
> 2014-03-19  Zhenqiang Chen  <zhenqiang.chen@linaro.org>
>
>      * gcc.target/arm/neon-modes-3.c: Add "-g" option.
>
> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
> index a68ed8d..c4466c1 100644
> --- a/gcc/config/arm/arm.c
> +++ b/gcc/config/arm/arm.c
> @@ -28692,7 +28692,7 @@ arm_dwarf_register_span (rtx rtl)
>   {
>     enum machine_mode mode;
>     unsigned regno;
> -  rtx parts[8];
> +  rtx parts[16];
>     int nregs;
>     int i;
>
> diff --git a/gcc/testsuite/gcc.target/arm/neon-modes-3.c
> b/gcc/testsuite/gcc.target/arm/neon-modes-3.c
> index fe81875..f3e4f33 100644
> --- a/gcc/testsuite/gcc.target/arm/neon-modes-3.c
> +++ b/gcc/testsuite/gcc.target/arm/neon-modes-3.c
> @@ -1,6 +1,6 @@
>   /* { dg-do compile } */
>   /* { dg-require-effective-target arm_neon_ok } */
> -/* { dg-options "-O" } */
> +/* { dg-options "-O -g" } */
>   /* { dg-add-options arm_neon } */
>
>   #include <arm_neon.h>


--
Ramana Radhakrishnan
Principal Engineer
ARM Ltd.