Re: [PATCH] PR59909, Fix powerpcle64 power8 bootstrap (quad memory support)

[David Edelsohn <dje dot gcc at gmail dot com>]

On Wed, Jan 22, 2014 at 1:50 PM, Michael Meissner
<meissner@linux.vnet.ibm.com> wrote:
> The current trunk will not bootstrap on a powerpcle64 power8 box if
> --with-cpu=power8 is selected.  This has been traced down to the fact that we
> did not swap the double words when we used the quad memory instructions.
>
> In this patch, I split the ISA 2.07 quad memory support into two parts, one for
> the non-atomic quad memory support instructions, and the other for atomic quad
> memory support.  In big endian systems, both forms are generated, while in
> little endian systems only the atomic instructions are generated, since the
> overhead of swapping the words would diminish the appeal of using the
> non-atomic quad memory instructions.
>
> At a future date, I would like to optimize the quad memory atomic instructions
> not to do the swapping in some cases.  That optimization is not in these
> patches.
>
> I'm attaching two versions of the patch.  The first version is against the
> current trunk.  The second version is against the 4.8 compiler in the IBM
> branch.
>
> This has been tested by doing a full bootstrap on a power8 box in little endian
> mode.  There are no regressions in the powerpc tests.  Is this patch ok to
> apply?
>
> 2014-01-22  Michael Meissner  <meissner@linux.vnet.ibm.com>
>
>         PR target/59909
>         * doc/invoke.texi (RS/6000 and PowerPC Options): Document
>         -mquad-memory-atomic.  Update -mquad-memory documentation to say
>         it is only used for non-atomic loads/stores.
>
>         * config/rs6000/predicates.md (quad_int_reg_operand): Allow either
>         -mquad-memory or -mquad-memory-atomic switches.
>
>         * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add
>         -mquad-memory-atomic to ISA 2.07 support.
>
>         * config/rs6000/rs6000.opt (-mquad-memory-atomic): Add new switch
>         to separate support of normal quad word memory operations (ldq,
>         stq) from the atomic quad word memory operations.
>
>         * config/rs6000/rs6000.c (rs6000_option_override_internal): Add
>         support to separate non-atomic quad word operations from atomic
>         quad word operations.  Disable non-atomic quad word operations in
>         little endian mode so that we don't have to swap words after the
>         load and before the store.
>         (quad_load_store_p): Add comment about atomic quad word support.
>         (rs6000_opt_masks): Add -mquad-memory-atomic.
>
>         * config/rs6000/rs6000.h (TARGET_SYNC_TI): Add support for
>         -mquad-memory-atomic.
>         (TARGET_SYNC_HI_QI): Likewise.
>
>         * config/rs6000/sync.md (qswap_pred1): Add support for swapping
>         double word registers with quad word atomic instructions in little
>         endian mode.
>         (qswap_pred2): Likewise.
>         (qswap_other): Likewise.
>         (qswap_<mode>): Likewise.
>         (load_lockedti): Likewise.
>         (load_lockedpti): Likewise.
>         (store_conditionalti): Likewise.
>         (store_conditionalpti): Likewise.
>
>         * gcc/config/rs6000/rs6000.md (UNSPEC_TI_PTI_SWAP): New UNSPEC for
>         dealing with quad word atomic instructions in little endian mode.
>
>         * gcc/config/rs6000/rs6000-c.c (rs6000_target_modify_macros):
>         Define __QUAD_MEMORY__ and __QUAD_MEMORY_ATOMIC__ based on what
>         type of quad memory support is available.

The patch is okay, but please clarify the sync.md ChangeLog to mention
what you did for the patterns, like new patterns, new attrs, which
patterns are changed to swap double words in LE mode.

Thanks, David