[PATCH, i386]: Fix PR56788, _mm_frcz_sd and _mm_frcz_ss ignore their second argument

[Uros Bizjak <ubizjak at gmail dot com>]

Hello!

Attached patch fixes PR56788, where _mm_frcz_{ss,sd} intrinsics
ignored their second argument.

As explained in the PR [1], gcc implements two-operand "vector-merge"
form as documented in Microsoft's definition [2]. However, in contrast
to other SSE scalar insns, the instruction itself clears upper bits to
zero.

There were a couple of problems: the builtin was declared as builtin
with two input operands, but the number of input operands didn't
correspond to referred insn pattern, leaving its second operand
uninitialized. The intrinsic was also implemented without necessary
movss/movsd fixup that would merge both its operands in a correct way.

Please also note that the definition in clang is wrong.

I didn't include any testcase in the patch, since I don't have access
to XOP target. Hopefully someone from AMD will provide tests that are
mysteriously missing from XOP testsuite.

2013-11-23  Uros Bizjak  <ubizjak@gmail.com>

    PR target/56788
    * config/i386/i386.c (bdesc_multi_arg) <IX86_BUILTIN_VFRCZSS>:
    Declare as MULTI_ARG_1_SF instruction.
    <IX86_BUILTIN_VFRCZSD>: Decleare as MULTI_ARG_1_DF instruction.
    * config/i386/sse.md (*xop_vmfrcz<mode>2): Rename
    from *xop_vmfrcz_<mode>.
    * config/i386/xopintrin.h (_mm_frcz_ss): Use __builtin_ia32_movss
    to merge scalar result with __A.
    (_mm_frcz_sd): Use __builtin_ia32_movsd to merge scalar
    result with __A.

Patch was bootstrapped and regression tested on x86_64-pc-linux-gnu {,-m32}.

The patch was committed to mainline SVN and will be committed to other
release branches in a couple of days (hopefully with additional
tests).

[1] http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56788
[2] http://msdn.microsoft.com/en-us/library/vstudio/gg445126%28v=vs.100%29.aspx

Uros.

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