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[RFC][LIBGCC][0 of 2] 64 bit divide implementation for processor without hw divide instruction
- From: Kugan <kugan dot vivekanandarajah at linaro dot org>
- To: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Cc: ian at airis dot com, Richard Earnshaw <Richard dot Earnshaw at arm dot com>, "patches at linaro dot org" <patches at linaro dot org>
- Date: Sat, 23 Nov 2013 12:46:42 +1100
- Subject: [RFC][LIBGCC][0 of 2] 64 bit divide implementation for processor without hw divide instruction
- Authentication-results: sourceware.org; auth=none
This RFC patch series implements a simple align divisor shift dividend
method for 64bit divide and enables for ARMv7-a.
This algorithm runs (K+1) times where K is the number of bits divisor is
shifted to align. I have done repeated divides and found that this
implementation performs better for processor without hw divide instruction.
On a chromebook, when K is large (close to 64) this performs on an
average ~10% faster. When K is small (8 to 24), it performs about ~100%
faster on an average.
Regression tested on arm-none-linux-gnueabi with no issues.