[RFC] [PATCH, AARCH64] Machine descriptions to support stack smashing protection

[Venkataramanan Kumar <venkataramanan dot kumar at linaro dot org>]

Hi Maintainers,

This is RFC patch that adds machine descriptions to support stack
smashing protection in AArch64.

I have written a very simple patch that prints "stack set" and "stack
test" as template of instructions.

I had 2 assumptions.

1) For "stack_protect_set" and "stack_protect_test", I
used "memory_operand" as predicate.

GCC pushes the memory operand in a register much
earlier during expand phase before these patterns are invoked.

So assuming that I will get a memory operand "__stack_chk_gaurd" in a
register when we are not using TLS based stack guard.

2) For the TLS case, assuming stack guard value will be stored at "-8"
offset from "tp" GCC generates below code for stack set.


        mrs     x0, tpidr_el0
        ldr     x1, [x0,-8]
        str     x1, [x29,24]
        mov     x1,0

I submitted Glibc patches some time before
https://sourceware.org/ml/libc-ports/2013-08/msg00044.html.

There are few regressions, the pthread_cancel tests in glibc fails I
am currently debugging :(.

GCC with the patch generates below code for stack test

        ldr     x1, [x29,24]
        ldr     x0, [x0,-8]
        eor     x0, x1, x0
        cbnz    x0, .L4
.................................
......................................
.L4:
        bl      __stack_chk_f


I generate "eor" since it has 2 purpose one for checking equality, and
 two  for clearing the canary loaded register.

Request your feedback to shape this into a better patch.

regards,
Venkat.

Attachment: libssp.aarch64.patch.txt
Description: Text document