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Re: [SH] PR 30807 - Add test case


On Wed, 2013-11-06 at 08:09 +0900, Kaz Kojima wrote:
> Oleg Endo <oleg.endo@t-online.de> wrote:
> > This adds a test case for PR 30807 which is based on the PR's attachment
> > 17961.  Tested with
> > make -k check-gcc RUNTESTFLAGS="sh-torture.exp --target_board=sh-sim
> > \{-m2/-ml,-m2/-mb,-m2a/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}
> > 
> > OK to add?
> 
> OK with the changes suggested by Mike and you.
> 
> > I can also fix the other existing SH tests to prevent further copy pasta
> > as a separate patch.
> 
> It's pre-approved.

I've committed the attached patch as rev 204487.

Cheers,
Oleg

testsuite/ChangeLog:
	* gcc.target/sh/pr51244-11.c: Remove target line.
	* gcc.target/sh/sh4a-sincosf.c: Likewise.
	* gcc.target/sh/attr-isr-trap_exit.c: Likewise.
	* gcc.target/sh/pr51244-15.c: Likewise.
	* gcc.target/sh/pr51244-19.c: Likewise.
	* gcc.target/sh/cmpstr.c: Likewise.
	* gcc.target/sh/pr33135-3.c: Likewise.
	* gcc.target/sh/pr53512-2.c: Likewise.
	* gcc.target/sh/pr54602-2.c: Likewise.
	* gcc.target/sh/pr52483-1.c: Likewise.
	* gcc.target/sh/pr21255-2-ml.c: Likewise.
	* gcc.target/sh/pr54760-4.c: Likewise.
	* gcc.target/sh/pr52483-5.c: Likewise.
	* gcc.target/sh/pr54089-2.c: Likewise.
	* gcc.target/sh/pr56547-2.c: Likewise.
	* gcc.target/sh/pr54089-6.c: Likewise.
	* gcc.target/sh/pr51244-20.c: Likewise.
	* gcc.target/sh/pr50749-sf-predec-4.c: Likewise.
	* gcc.target/sh/sh4a-fsrra.c: Likewise.
	* gcc.target/sh/pr50749-qihisi-predec-1.c: Likewise.
	* gcc.target/sh/pr50749-sf-postinc-2.c: Likewise.
	* gcc.target/sh/pr55303-2.c: Likewise.
	* gcc.target/sh/sh2a-resbank.c: Likewise.
	* gcc.target/sh/sp-switch.c: Likewise.
	* gcc.target/sh/pr51244-3.c: Likewise.
	* gcc.target/sh/pr50751-3.c: Likewise.
	* gcc.target/sh/pr51244-7.c: Likewise.
	* gcc.target/sh/struct-arg-dw2.c: Likewise.
	* gcc.target/sh/pr50751-7.c: Likewise.
	* gcc.target/sh/pr49468-di.c: Likewise.
	* gcc.target/sh/pr50749-qihisi-postinc-4.c: Likewise.
	* gcc.target/sh/pr49880-3.c: Likewise.
	* gcc.target/sh/pr51244-12.c: Likewise.
	* gcc.target/sh/pr53988.c: Likewise.
	* gcc.target/sh/pr6526.c: Likewise.
	* gcc.target/sh/sh2a-bxor.c: Likewise.
	* gcc.target/sh/pr51244-16.c: Likewise.
	* gcc.target/sh/sh2a-bclrmem.c: Likewise.
	* gcc.target/sh/sh2a-bor.c: Likewise.
	* gcc.target/sh/pr53511-1.c: Likewise.
	* gcc.target/sh/pr21255-3.c: Likewise.
	* gcc.target/sh/pr53512-3.c: Likewise.
	* gcc.target/sh/pr33135-4.c: Likewise.
	* gcc.target/sh/pr54602-3.c: Likewise.
	* gcc.target/sh/pr54760-1.c: Likewise.
	* gcc.target/sh/pr52483-2.c: Likewise.
	* gcc.target/sh/sh2a-bsetmem.c: Likewise.
	* gcc.target/sh/pr54680.c: Likewise.
	* gcc.target/sh/pr54386.c: Likewise.
	* gcc.target/sh/pr51244-20-sh2a.c: Likewise.
	* gcc.target/sh/pr54089-3.c: Likewise.
	* gcc.target/sh/pr50749-sf-predec-1.c: Likewise.
	* gcc.target/sh/pr54089-7.c: Likewise.
	* gcc.target/sh/strlen.c: Likewise.
	* gcc.target/sh/pr50749-sf-postinc-3.c: Likewise.
	* gcc.target/sh/pr50749-qihisi-predec-2.c: Likewise.
	* gcc.target/sh/pr55303-3.c: Likewise.
	* gcc.target/sh/pr51244-4.c: Likewise.
	* gcc.target/sh/pr50751-4.c: Likewise.
	* gcc.target/sh/pr39423-1.c: Likewise.
	* gcc.target/sh/pr51244-8.c: Likewise.
	* gcc.target/sh/pr55146.c: Likewise.
	* gcc.target/sh/pr50751-8.c: Likewise.
	* gcc.target/sh/sh2a-bset.c: Likewise.
	* gcc.target/sh/pr50749-qihisi-postinc-1.c: Likewise.
	* gcc.target/sh/sh2a-movi20s.c: Likewise.
	* gcc.target/sh/20080410-1.c: Likewise.
	* gcc.target/sh/pr49880-4.c: Likewise.
	* gcc.target/sh/pr51244-13.c: Likewise.
	* gcc.target/sh/sh2a-movrt.c: Likewise.
	* gcc.target/sh/pr51244-17.c: Likewise.
	* gcc.target/sh/pr21255-2-mb.c: Likewise.
	* gcc.target/sh/sh2a-bclr.c: Likewise.
	* gcc.target/sh/pr33135-1.c: Likewise.
	* gcc.target/sh/pr53512-4.c: Likewise.
	* gcc.target/sh/pr54602-4.c: Likewise.
	* gcc.target/sh/sh4a-bitmovua.c: Likewise.
	* gcc.target/sh/pr54760-2.c: Likewise.
	* gcc.target/sh/pr52483-3.c: Likewise.
	* gcc.target/sh/sh2a-bld.c: Likewise.
	* gcc.target/sh/pr54089-4.c: Likewise.
	* gcc.target/sh/pr54685.c: Likewise.
	* gcc.target/sh/pr50749-sf-predec-2.c: Likewise.
	* gcc.target/sh/pr54089-8.c: Likewise.
	* gcc.target/sh/pragma-isr-trap-exit.c: Likewise.
	* gcc.target/sh/pr50749-qihisi-predec-3.c: Likewise.
	* gcc.target/sh/pr50749-sf-postinc-4.c: Likewise.
	* gcc.target/sh/pr51244-1.c: Likewise.
	* gcc.target/sh/pr50751-1.c: Likewise.
	* gcc.target/sh/pr55160.c: Likewise.
	* gcc.target/sh/pr51244-5.c: Likewise.
	* gcc.target/sh/pr54236-1.c: Likewise.
	* gcc.target/sh/pr50751-5.c: Likewise.
	* gcc.target/sh/pr52933-1.c: Likewise.
	* gcc.target/sh/pr39423-2.c: Likewise.
	* gcc.target/sh/pr51244-9.c: Likewise.
	* gcc.target/sh/pr49263.c: Likewise.
	* gcc.target/sh/pr50749-qihisi-postinc-2.c: Likewise.
	* gcc.target/sh/pr49880-1.c: Likewise.
	* gcc.target/sh/sh2a-band.c: Likewise.
	* gcc.target/sh/pr51244-10.c: Likewise.
	* gcc.target/sh/pr49880-5.c: Likewise.
	* gcc.target/sh/prefetch.c: Likewise.
	* gcc.target/sh/pr51244-14.c: Likewise.
	* gcc.target/sh/rte-delay-slot.c: Likewise.
	* gcc.target/sh/fpul-usage-1.c: Likewise.
	* gcc.target/sh/pr51244-18.c: Likewise.
	* gcc.target/sh/pr21255-1.c: Likewise.
	* gcc.target/sh/pr33135-2.c: Likewise.
	* gcc.target/sh/pr53512-1.c: Likewise.
	* gcc.target/sh/pr54602-1.c: Likewise.
	* gcc.target/sh/sh2a-rtsn.c: Likewise.
	* gcc.target/sh/torture/pragma-isr.c: Likewise.
	* gcc.target/sh/torture/pragma-isr2.c: Likewise.
	* gcc.target/sh/torture/pr58314.c: Likewise.
	* gcc.target/sh/torture/pr34777.c: Likewise.
	* gcc.target/sh/torture/pr58475.c: Likewise.
	* gcc.target/sh/pr54760-3.c: Likewise.
	* gcc.target/sh/sh4a-cosf.c: Likewise.
	* gcc.target/sh/pr52483-4.c: Likewise.
	* gcc.target/sh/mfmovd.c: Likewise.
	* gcc.target/sh/pr54089-1.c: Likewise.
	* gcc.target/sh/pr56547-1.c: Likewise.
	* gcc.target/sh/pr54089-5.c: Likewise.
	* gcc.target/sh/pr50749-sf-predec-3.c: Likewise.
	* gcc.target/sh/pr54089-9.c: Likewise.
	* gcc.target/sh/sh2a-jsrn.c: Likewise.
	* gcc.target/sh/pr49468-si.c: Likewise.
	* gcc.target/sh/pr50749-sf-postinc-1.c: Likewise.
	* gcc.target/sh/pr50749-qihisi-predec-4.c: Likewise.
	* gcc.target/sh/pr55303-1.c: Likewise.
	* gcc.target/sh/pr51244-2.c: Likewise.
	* gcc.target/sh/pr50751-2.c: Likewise.
	* gcc.target/sh/pr54236-2.c: Likewise.
	* gcc.target/sh/pr51244-6.c: Likewise.
	* gcc.target/sh/cmpstrn.c: Likewise.
	* gcc.target/sh/pr50751-6.c: Likewise.
	* gcc.target/sh/pr52933-2.c: Likewise.
	* gcc.target/sh/pr53568-1.c: Likewise.
	* gcc.target/sh/pr50749-qihisi-postinc-3.c: Likewise.
	* gcc.target/sh/sh2a-tbr-jump.c: Likewise.
	* gcc.target/sh/sh4a-sinf.c: Likewise.
	* gcc.target/sh/pr49880-2.c: Likewise.

Index: gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-3.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-3.c	(working copy)
@@ -1,6 +1,6 @@
 /* PR target/50749: Verify that pre-decrement addressing is generated
    inside a loop.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-final { scan-assembler-times "mov.b\tr\[0-9]\+,@-r\[0-9]\+" 1 } } */
 /* { dg-final { scan-assembler-times "mov.w\tr\[0-9]\+,@-r\[0-9]\+" 1 } } */
Index: gcc/testsuite/gcc.target/sh/pr55303-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr55303-3.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr55303-3.c	(working copy)
@@ -1,6 +1,6 @@
 /* Verify that the special case (umin (reg const_int 1)) results in the
    expected instruction sequence on SH2A.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
 /* { dg-final { scan-assembler-times "tst" 1 } } */
Index: gcc/testsuite/gcc.target/sh/pr55160.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr55160.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr55160.c	(working copy)
@@ -1,5 +1,5 @@
 /* Check that the decrement-and-test instruction is generated.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "dt\tr" 2 } } */
Index: gcc/testsuite/gcc.target/sh/pr51244-4.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-4.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr51244-4.c	(working copy)
@@ -1,7 +1,7 @@
 /* Check that storing the (negated) T bit as all ones or zeros in a reg
    uses the subc instruction.  On SH2A a sequence with the movrt instruction
    is also OK instead of subc.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1 -mbranch-cost=2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
 /* { dg-final { scan-assembler-not "movt|tst|negc" } } */
Index: gcc/testsuite/gcc.target/sh/pr50751-4.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50751-4.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50751-4.c	(working copy)
@@ -1,7 +1,7 @@
 /* Check that the mov.w displacement addressing insn is generated.
    If the insn is generated as expected, there should be no address 
    calculations outside the mov insns.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
 /* { dg-final { scan-assembler-not "add|sub" } } */
Index: gcc/testsuite/gcc.target/sh/pr39423-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr39423-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr39423-1.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that displacement addressing is used for indexed addresses with a
    small offset, instead of re-calculating the index.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
 /* { dg-final { scan-assembler-not "add\t#1" } } */
Index: gcc/testsuite/gcc.target/sh/pr21255-2-ml.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr21255-2-ml.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr21255-2-ml.c	(working copy)
@@ -1,4 +1,4 @@
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2 -fomit-frame-pointer" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-mb" && "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler "mov @\\(4,r.\\),r.; mov @r.,r." } } */
Index: gcc/testsuite/gcc.target/sh/pr51244-8.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-8.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr51244-8.c	(working copy)
@@ -6,7 +6,7 @@
 	tst	#1,r0
 	bf	.L47
 */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "shad|neg" } } */
Index: gcc/testsuite/gcc.target/sh/mfmovd.c
===================================================================
--- gcc/testsuite/gcc.target/sh/mfmovd.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/mfmovd.c	(working copy)
@@ -1,6 +1,6 @@
 /* Verify that we generate fmov.d instructions to move doubles when -mfmovd 
    option is enabled.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-require-effective-target hard_float } */
 /* { dg-options "-mfmovd" } */
 /* { dg-skip-if "" { *-*-* }  { "*-single-only" } { "" } } */
Index: gcc/testsuite/gcc.target/sh/pr50751-8.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50751-8.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50751-8.c	(working copy)
@@ -1,7 +1,7 @@
 /* Check that on SH2A the 4 byte movu.b and movu.w displacement insns are
    generated.  This has to be checked with -O2 because some of the patterns
    rely on peepholes.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
 /* { dg-final { scan-assembler-times "movu.b" 4 } } */
Index: gcc/testsuite/gcc.target/sh/sh2a-bset.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-bset.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/sh2a-bset.c	(working copy)
@@ -1,6 +1,6 @@
 /* Testcase to check generation of a SH2A specific instruction
   'BSET #imm3,Rn'.  */
-/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-do assemble }  */
 /* { dg-options "-O1" }  */
 /* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "bset"} }  */
Index: gcc/testsuite/gcc.target/sh/pr49263.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr49263.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr49263.c	(working copy)
@@ -2,7 +2,7 @@
    allows it.  Under some circumstances another compare instruction might
    be selected, which is also fine.  Any AND instructions are considered
    counter productive and fail the test.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-final { scan-assembler-not "and" } } */
 
Index: gcc/testsuite/gcc.target/sh/sh2a-tbr-jump.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-tbr-jump.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/sh2a-tbr-jump.c	(working copy)
@@ -1,6 +1,6 @@
 /* Testcase to check generation of a SH2A specific,
    TBR relative jump instruction - 'JSR @@(disp8,TBR)'.  */
-/* { dg-do assemble {target sh*-*-*}} */
+/* { dg-do assemble }  */
 /* { dg-options "" } */
 /* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */
 /* { dg-final { scan-assembler-times "jsr/n\\t@@\\(40,tbr\\)" 1} } */
Index: gcc/testsuite/gcc.target/sh/sh2a-bld.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-bld.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/sh2a-bld.c	(working copy)
@@ -4,7 +4,7 @@
     BLD #imm3, Rn
     BLD.B #imm3, @(disp12, Rn)
  */
-/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-do assemble }  */
 /* { dg-options "-Os -mbitops" }  */
 /* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "bld"} }  */
Index: gcc/testsuite/gcc.target/sh/pr49880-4.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr49880-4.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr49880-4.c	(working copy)
@@ -1,7 +1,7 @@
 /* Check that the option -mdiv=call-fp does not produce calls to the
    library function that uses FPU to implement integer division if FPU insns
    are not supported or are disabled.  */
-/* { dg-do compile { target "sh*-*-*" } }  */
+/* { dg-do compile }  */
 /* { dg-options "-mdiv=call-fp" }  */
 /* { dg-skip-if "" { "sh*-*-*" } { "*"} { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" } }  */
 /* { dg-final { scan-assembler-not "sdivsi3_i4\n|udivsi3_i4\n" } }  */
Index: gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-2.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-2.c	(working copy)
@@ -1,6 +1,6 @@
 /* PR target/50749: Verify that subsequent post-increment addressings
    are generated.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fmov.s\t@r\[0-9]\+\\+,fr\[0-9]\+" 5 { xfail *-*-*} } } */
Index: gcc/testsuite/gcc.target/sh/sh2a-bclr.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-bclr.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/sh2a-bclr.c	(working copy)
@@ -1,6 +1,6 @@
 /* Testcase to check generation of a SH2A specific instruction
    'BCLR #imm3,Rn'.  */
-/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-do assemble }  */
 /* { dg-options "-O1" }  */
 /* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "bclr"} }  */
Index: gcc/testsuite/gcc.target/sh/pr33135-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr33135-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr33135-1.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that fcmp/eq and fcmp/gt instructions are generated by default
    (implicit -mieee).  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fcmp/eq" 4 } } */
Index: gcc/testsuite/gcc.target/sh/sh2a-resbank.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-resbank.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/sh2a-resbank.c	(working copy)
@@ -1,5 +1,5 @@
 /* Test for resbank attribute.  */
-/* { dg-do assemble {target sh*-*-*}} */
+/* { dg-do assemble }  */
 /* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */
 /* { dg-final { scan-assembler "resbank" } } */
  
Index: gcc/testsuite/gcc.target/sh/pr53512-4.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr53512-4.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr53512-4.c	(working copy)
@@ -1,6 +1,6 @@
 /* Verify that the fsrra insn is not used when specifying -mno-fsrra and
   -funsafe-math-optimizations and -ffinite-math-only.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1 -mno-fsrra -funsafe-math-optimizations -ffinite-math-only" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-not "fsrra" } } */
Index: gcc/testsuite/gcc.target/sh/pr54602-4.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54602-4.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr54602-4.c	(working copy)
@@ -1,7 +1,7 @@
 /* Verify that the delay slot is stuffed with register pop insns on SH3* and
    SH4* targets, where the stack pointer is not used by the rte insn.  If
    everything works out, we won't see a nop insn.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m3*" "-m4*" } }  */
 /* { dg-final { scan-assembler-not "nop" } } */
Index: gcc/testsuite/gcc.target/sh/pr54760-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54760-2.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr54760-2.c	(working copy)
@@ -1,7 +1,7 @@
 /* Check that thread pointer relative memory accesses are converted to
    gbr displacement address modes.  If we see a gbr register store
    instruction something is not working properly.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "stc\tgbr" 0 } } */
Index: gcc/testsuite/gcc.target/sh/pr52483-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr52483-3.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr52483-3.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that loads/stores from/to volatile mems utilize indexed addressing
    modes and do not result in redundant sign/zero extensions. */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "@\\(r0," 6 } } */
Index: gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-2.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-2.c	(working copy)
@@ -1,6 +1,6 @@
 /* PR target/50749: Verify that subsequent post-increment addressings
    are generated.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-final { scan-assembler-times "mov.b\t@r\[0-9]\+\\+,r\[0-9]\+" 5 { xfail *-*-*} } } */
 /* { dg-final { scan-assembler-times "mov.w\t@r\[0-9]\+\\+,r\[0-9]\+" 5 { xfail *-*-*} } } */
Index: gcc/testsuite/gcc.target/sh/pr54089-4.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54089-4.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr54089-4.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that the rotcr instruction is generated when shifting the
    negated T bit on non-SH2A.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } }  */
 /* { dg-final { scan-assembler-times "rotcr" 1 } } */
Index: gcc/testsuite/gcc.target/sh/20080410-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/20080410-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/20080410-1.c	(working copy)
@@ -1,4 +1,4 @@
-/* { dg-do compile { target "sh-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O0" } */
 /* { dg-skip-if "" { "sh*-*-*" } "-mb" "" }  */
 /* { dg-final { scan-assembler-not "add\tr0,r0" } } */
Index: gcc/testsuite/gcc.target/sh/pr50749-sf-predec-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-sf-predec-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50749-sf-predec-1.c	(working copy)
@@ -1,5 +1,5 @@
 /* PR target/50749: Verify that pre-decrement addressing is generated.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fmov.s\tfr\[0-9]\+,@-r\[0-9]\+" 1 } } */
Index: gcc/testsuite/gcc.target/sh/pr54089-8.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54089-8.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr54089-8.c	(working copy)
@@ -1,5 +1,5 @@
 /* Check that the rotcl instruction is generated.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "rotcl" 28 } } */
Index: gcc/testsuite/gcc.target/sh/prefetch.c
===================================================================
--- gcc/testsuite/gcc.target/sh/prefetch.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/prefetch.c	(working copy)
@@ -1,6 +1,6 @@
 /* Testcase to check generation of a SH4 and SH2A operand cache prefetch
    instruction PREF @Rm.  */
-/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-do assemble }  */
 /* { dg-options "-O0" }  */
 /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" "-m3*" "-m4*" } }  */
 /* { dg-final { scan-assembler "pref"} }  */
Index: gcc/testsuite/gcc.target/sh/pr51244-13.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-13.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr51244-13.c	(working copy)
@@ -8,7 +8,7 @@
    branch condition.  The tested function contains two other tst insns.  If
    everything goes as expected we will be seeing only those other two tst
    insns.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-times "tst" 2 } } */
Index: gcc/testsuite/gcc.target/sh/sh2a-movrt.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-movrt.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/sh2a-movrt.c	(working copy)
@@ -1,6 +1,6 @@
 /* Testcase to check generation of a SH2A specific instruction for
    'MOVRT Rn'.  */
-/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-do assemble }  */
 /* { dg-options "-O1" }  */
 /* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "movrt"} }  */
Index: gcc/testsuite/gcc.target/sh/pr51244-17.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-17.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr51244-17.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that no unnecessary zero extensions are done on values that are
    results of arithmetic with T bit inputs.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "extu|exts" } } */
Index: gcc/testsuite/gcc.target/sh/cmpstr.c
===================================================================
--- gcc/testsuite/gcc.target/sh/cmpstr.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/cmpstr.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that the __builtin_strcmp function is inlined with cmp/str
    when optimizing for speed.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "jmp" } } */
Index: gcc/testsuite/gcc.target/sh/sh2a-bclrmem.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-bclrmem.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/sh2a-bclrmem.c	(working copy)
@@ -1,6 +1,6 @@
 /* Testcase to check generation of a SH2A specific instruction
    "BCLR #imm3,@(disp12,Rn)".  */
-/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-do assemble }  */
 /* { dg-options "-O2 -mbitops" }  */
 /* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "bclr"} }  */
Index: gcc/testsuite/gcc.target/sh/pr51244-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr51244-1.c	(working copy)
@@ -1,7 +1,7 @@
 /* Check that inverted conditional branch logic does not generate
    unnecessary explicit T bit extractions, inversions and 
    test instructions.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1 -mbranch-cost=2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
 /* { dg-final { scan-assembler-not "movt|tst|negc|extu" } } */
Index: gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-4.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-4.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-4.c	(working copy)
@@ -1,6 +1,6 @@
 /* PR target/50749: Verify that pre-decrement addressing is generated
    inside a loop.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-final { scan-assembler-times "mov.b\tr\[0-9]\+,@-r\[0-9]\+" 3 { xfail *-*-*} } } */
 /* { dg-final { scan-assembler-times "mov.w\tr\[0-9]\+,@-r\[0-9]\+" 3 { xfail *-*-*} } } */
Index: gcc/testsuite/gcc.target/sh/pr50751-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50751-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50751-1.c	(working copy)
@@ -1,7 +1,7 @@
 /* Check that the mov.b displacement addressing insn is generated.
    If the insn is generated as expected, there should be no address 
    calculations outside the mov insns.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
 /* { dg-final { scan-assembler-not "add|sub" } } */
Index: gcc/testsuite/gcc.target/sh/pr51244-5.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-5.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr51244-5.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that no unnecessary sign or zero extension insn is generated after
    a negc or movrt insn that stores the inverted T bit in a reg.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "extu|exts" } } */
Index: gcc/testsuite/gcc.target/sh/pr54236-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54236-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr54236-1.c	(working copy)
@@ -1,7 +1,7 @@
 /* Tests to check the utilization of addc, subc and negc instructions in
    special cases.  If everything works as expected we won't see any
    movt instructions in these cases.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
 /* { dg-final { scan-assembler-times "addc" 4 } } */
Index: gcc/testsuite/gcc.target/sh/pr50751-5.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50751-5.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50751-5.c	(working copy)
@@ -2,7 +2,7 @@
    base address is adjusted only once.  On SH2A this test is skipped because
    there is a 4 byte mov.w insn that can handle larger displacements.  Thus
    on SH2A the base address will not be adjusted in this case.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */
 /* { dg-final { scan-assembler-times "add" 2 } } */
Index: gcc/testsuite/gcc.target/sh/pr52933-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr52933-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr52933-1.c	(working copy)
@@ -2,7 +2,7 @@
    Each test case is expected to emit at least one div0s insn.
    Problems when combining the div0s comparison result with surrounding
    logic usually show up as redundant tst insns.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-times "div0s" 25 } } */
Index: gcc/testsuite/gcc.target/sh/pr39423-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr39423-2.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr39423-2.c	(working copy)
@@ -1,7 +1,7 @@
 /* Check that displacement addressing is used for indexed addresses with a
    small offset, instead of re-calculating the index and that the movu.w
    instruction is used on SH2A.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
 /* { dg-final { scan-assembler-not "add\t#1" } } */
Index: gcc/testsuite/gcc.target/sh/cmpstrn.c
===================================================================
--- gcc/testsuite/gcc.target/sh/cmpstrn.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/cmpstrn.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that the __builtin_strncmp function is inlined
    when optimizing for speed.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "jmp" } } */
Index: gcc/testsuite/gcc.target/sh/pr51244-9.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-9.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr51244-9.c	(working copy)
@@ -8,7 +8,7 @@
 	cmp/hi	r2,r7			bt	.L534
 	bf	.L534
 */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "mov\t#0" } } */
Index: gcc/testsuite/gcc.target/sh/sh2a-bsetmem.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-bsetmem.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/sh2a-bsetmem.c	(working copy)
@@ -1,6 +1,6 @@
 /* Testcase to check generation of a SH2A specific instruction
    "BSET #imm3,@(disp12,Rn)".  */
-/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-do assemble }  */
 /* { dg-options "-O2 -mbitops" }  */
 /* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "bset"} }  */
Index: gcc/testsuite/gcc.target/sh/pr49880-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr49880-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr49880-1.c	(working copy)
@@ -1,5 +1,5 @@
 /* Check that the option -mdiv=call-div1 works.  */
-/* { dg-do link { target "sh*-*-*" } } */
+/* { dg-do link }  */
 /* { dg-options "-mdiv=call-div1" }  */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 
Index: gcc/testsuite/gcc.target/sh/sh2a-band.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-band.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/sh2a-band.c	(working copy)
@@ -1,6 +1,6 @@
 /* Testcase to check generation of a SH2A specific instruction for
    "BAND.B #imm3, @(disp12, Rn)".  */
-/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-do assemble }  */
 /* { dg-options "-O1 -mbitops" }  */
 /* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "band.b"} }  */
Index: gcc/testsuite/gcc.target/sh/pr49880-5.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr49880-5.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr49880-5.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that the option -mdiv=call-fp results in the corresponding library
    function calls on targets that have a double precision FPU.  */
-/* { dg-do compile { target "sh*-*-*" } }  */
+/* { dg-do compile }  */
 /* { dg-options "-mdiv=call-fp" }  */
 /* { dg-skip-if "" { "sh*-*-*" } { "*"} { "-m2a" "-m4" "-m4a" "*single-only" } }  */
 /* { dg-final { scan-assembler "sdivsi3_i4\n" } }  */
Index: gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-3.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-3.c	(working copy)
@@ -1,6 +1,6 @@
 /* PR target/50749: Verify that post-increment addressing is generated
    inside a loop.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fmov.s\t@r\[0-9]\+\\+,fr\[0-9]\+" 1 } } */
Index: gcc/testsuite/gcc.target/sh/pr21255-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr21255-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr21255-1.c	(working copy)
@@ -1,4 +1,4 @@
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2 -fomit-frame-pointer" } */
 /* { dg-final { scan-assembler "mov fr4,fr.; mov fr5,fr." { target sh-*-* } } } */
 /* { dg-final { scan-assembler "mov fr4,fr.; mov fr5,fr." { target sh[1234lb]*-*-* } } } */
Index: gcc/testsuite/gcc.target/sh/pr33135-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr33135-2.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr33135-2.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that only the fcmp/gt instruction is generated when specifying
    -ffinite-math-only (implicit -mno-ieee).  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1 -ffinite-math-only" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-not "fcmp/eq" } } */
Index: gcc/testsuite/gcc.target/sh/pr53512-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr53512-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr53512-1.c	(working copy)
@@ -1,6 +1,6 @@
 /* Verify that the fsca insn is used when specifying -mfsca and
   -funsafe-math-optimizations.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1 -mfsca -funsafe-math-optimizations" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m3*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fsca" 3 } } */
Index: gcc/testsuite/gcc.target/sh/pr54602-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54602-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr54602-1.c	(working copy)
@@ -1,7 +1,7 @@
 /* Verify that the delay slot is stuffed with register pop insns for normal
    (i.e. not interrupt handler) function returns.  If everything goes as
    expected we won't see any nop insns.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-not "nop" } } */
Index: gcc/testsuite/gcc.target/sh/sh2a-rtsn.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-rtsn.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/sh2a-rtsn.c	(working copy)
@@ -1,6 +1,6 @@
 /* Testcase to check generation of a SH2A specific instruction for
    'RTS/N'.  */
-/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-do assemble }  */
 /* { dg-options "-O0" }  */
 /* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "rts/n"} }  */
Index: gcc/testsuite/gcc.target/sh/struct-arg-dw2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/struct-arg-dw2.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/struct-arg-dw2.c	(working copy)
@@ -1,6 +1,6 @@
 /* Verify that we don't generate frame related insn against stack adjustment
    for the object sent partially in registers. */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-g" } */
 /* { dg-final { scan-assembler-not "\t.cfi_def_cfa_offset 16" } } */
 
Index: gcc/testsuite/gcc.target/sh/pr54760-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54760-3.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr54760-3.c	(working copy)
@@ -2,7 +2,7 @@
    surrounding code.
    These should be moved to C torture tests once there are target
    independent thread_pointer built-in functions available.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 
Index: gcc/testsuite/gcc.target/sh/sh4a-cosf.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh4a-cosf.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/sh4a-cosf.c	(working copy)
@@ -1,6 +1,6 @@
 /* Verify that we generate single-precision sine and cosine approximate
    (fsca) in fast math mode on SH4A with FPU.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O -ffast-math" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } }  */
 /* { dg-final { scan-assembler "fsca" } } */
Index: gcc/testsuite/gcc.target/sh/pr52483-4.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr52483-4.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr52483-4.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that loads/stores from/to volatile floating point mems utilize
    indexed addressing modes. */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "@\\(r0," 2 } } */
Index: gcc/testsuite/gcc.target/sh/pr54089-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54089-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr54089-1.c	(working copy)
@@ -1,5 +1,5 @@
 /* Check that the rotcr instruction is generated.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "rotcr" 24 } } */
Index: gcc/testsuite/gcc.target/sh/pr56547-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr56547-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr56547-1.c	(working copy)
@@ -1,7 +1,7 @@
 /* Verify that the fmac insn is used for the expression 'a * b + a' and
    'a * a + a'.
    This assumes that the default compiler setting is -ffp-contract=fast.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fmac" 2 } } */
Index: gcc/testsuite/gcc.target/sh/sh2a-movi20s.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-movi20s.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/sh2a-movi20s.c	(working copy)
@@ -1,5 +1,5 @@
 /* Testcase to check generation of 'MOVI20S #imm20, Rn'.  */
-/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-do assemble }  */
 /* { dg-options "-O0" } */
 /* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "movi20s"} }  */
Index: gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-3.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-3.c	(working copy)
@@ -1,6 +1,6 @@
 /* PR target/50749: Verify that post-increment addressing is generated
    inside a loop.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-final { scan-assembler-times "mov.b\t@r\[0-9]\+\\+,r\[0-9]\+" 1 } } */
 /* { dg-final { scan-assembler-times "mov.w\t@r\[0-9]\+\\+,r\[0-9]\+" 1 } } */
Index: gcc/testsuite/gcc.target/sh/pr54089-5.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54089-5.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr54089-5.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that the movrt rotr instruction sequence is generated when shifting
    the negated T bit on SH2A.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
 /* { dg-final { scan-assembler-times "movrt" 1 } } */
Index: gcc/testsuite/gcc.target/sh/pr50749-sf-predec-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-sf-predec-2.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50749-sf-predec-2.c	(working copy)
@@ -1,6 +1,6 @@
 /* PR target/50749: Verify that subsequent pre-decrement addressings
    are generated.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fmov.s\tfr\[0-9]\+,@-r\[0-9]\+" 5 { xfail *-*-*} } } */
Index: gcc/testsuite/gcc.target/sh/pr51244-10.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-10.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr51244-10.c	(working copy)
@@ -10,7 +10,7 @@
 	tst	r0,r0
 	bt	.L195
 */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "shll|subc|and" } } */
Index: gcc/testsuite/gcc.target/sh/pr54089-9.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54089-9.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr54089-9.c	(working copy)
@@ -1,5 +1,5 @@
 /* Check that the rotcr instruction is generated.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "rotcl" 4 } } */
Index: gcc/testsuite/gcc.target/sh/pr51244-14.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-14.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr51244-14.c	(working copy)
@@ -9,7 +9,7 @@
 	bf/s	.L35
    where the negated T bit store did not combine properly.  Since there are
    other movt insns we only check for the xor and the extu.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "xor|extu" } } */
Index: gcc/testsuite/gcc.target/sh/pr6526.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr6526.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr6526.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that the XF registers are not clobbered by an integer division
    that is done using double precision FPU division.  */
-/* { dg-do run { target "sh*-*-*" } }  */
+/* { dg-do run }  */
 /* { dg-options "-O1 -mdiv=call-fp" }  */
 /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4*-single" "-m4*-single-only" } }  */
 
Index: gcc/testsuite/gcc.target/sh/sh2a-jsrn.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-jsrn.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/sh2a-jsrn.c	(working copy)
@@ -1,6 +1,6 @@
 /* Testcase to check generation of a SH2A specific instruction for
    'JSR/N @Rm'.  */
-/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-do assemble }  */
 /* { dg-options "-O0" }  */
 /* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "jsr/n"} }  */
Index: gcc/testsuite/gcc.target/sh/pr51244-18.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-18.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr51244-18.c	(working copy)
@@ -12,7 +12,7 @@
    not working as expected.  This test requires -O2 because the T bit stores
    in question will be eliminated in additional insn split passes after
    reload.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "movt|tst" } } */
Index: gcc/testsuite/gcc.target/sh/pr21255-2-mb.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr21255-2-mb.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr21255-2-mb.c	(working copy)
@@ -1,4 +1,4 @@
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-mb -O2 -fomit-frame-pointer" } */
 /* { dg-final { scan-assembler "mov @r.,r.; mov @\\(4,r.\\),r." } } */
 double d;
Index: gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-1.c	(working copy)
@@ -1,5 +1,5 @@
 /* PR target/50749: Verify that pre-decrement addressing is generated.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-final { scan-assembler-times "mov.b\tr\[0-9]\+,@-r\[0-9]\+" 1 { xfail *-*-*} } } */
 /* { dg-final { scan-assembler-times "mov.w\tr\[0-9]\+,@-r\[0-9]\+" 1 { xfail *-*-*} } } */
Index: gcc/testsuite/gcc.target/sh/pr55303-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr55303-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr55303-1.c	(working copy)
@@ -1,6 +1,6 @@
 /* Verify that the SH2A clips and clipu instructions are generated as
    expected.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
 /* { dg-final { scan-assembler-times "clips.b" 2 } } */
Index: gcc/testsuite/gcc.target/sh/pr51244-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-2.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr51244-2.c	(working copy)
@@ -2,7 +2,7 @@
    instruction pattern, the constant -1 is loaded only once.
    On SH2A this test is skipped because the movrt instruction is used
    to get the complement of the T bit.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1 -mbranch-cost=2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */
 /* { dg-final { scan-assembler-times "mov\t#-1" 1 } } */
Index: gcc/testsuite/gcc.target/sh/pr50751-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50751-2.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50751-2.c	(working copy)
@@ -2,7 +2,7 @@
    base address is adjusted only once.  On SH2A this test is skipped because
    there is a 4 byte mov.b insn that can handle larger displacements.  Thus
    on SH2A the base address will not be adjusted in this case.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */
 /* { dg-final { scan-assembler-times "add" 2 } } */
Index: gcc/testsuite/gcc.target/sh/pr54236-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54236-2.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr54236-2.c	(working copy)
@@ -1,7 +1,7 @@
 /* Tests to check the utilization of the addc instruction in special cases.
    If everything works as expected we won't see any movt instructions in
    these cases.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
 /* { dg-final { scan-assembler-times "addc" 37 } } */
Index: gcc/testsuite/gcc.target/sh/pr51244-6.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-6.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr51244-6.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that no unnecessary sign or zero extension insn is generated after
    a negc or movrt insn that stores the inverted T bit in a reg.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-not "extu|exts" } } */
Index: gcc/testsuite/gcc.target/sh/pr50751-6.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50751-6.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50751-6.c	(working copy)
@@ -1,7 +1,7 @@
 /* Check that on SH2A the 4 byte mov.w displacement insn is generated to
    handle larger displacements.  If it is generated correctly, there should
    be no base address adjustments outside the mov.w insns.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
 /* { dg-final { scan-assembler-not "add|sub" } } */
Index: gcc/testsuite/gcc.target/sh/pr52933-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr52933-2.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr52933-2.c	(working copy)
@@ -3,7 +3,7 @@
    Each test case is expected to emit at least one div0s insn.
    Problems when combining the div0s comparison result with surrounding
    logic usually show up as redundant tst insns.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2 -mpretend-cmove" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-times "div0s" 25 } } */
Index: gcc/testsuite/gcc.target/sh/pr53568-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr53568-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr53568-1.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that the bswap32 pattern is generated as swap.b and swap.w
    instructions.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "swap.w" 7 } } */
Index: gcc/testsuite/gcc.target/sh/sh4a-sinf.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh4a-sinf.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/sh4a-sinf.c	(working copy)
@@ -1,6 +1,6 @@
 /* Verify that we generate single-precision sine and cosine approximate
    (fsca) in fast math mode on SH4A with FPU.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O -ffast-math" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } }  */
 /* { dg-final { scan-assembler "fsca" } } */
Index: gcc/testsuite/gcc.target/sh/pr49880-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr49880-2.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr49880-2.c	(working copy)
@@ -1,5 +1,5 @@
 /* Check that the option -mdiv=call-fp works.  */
-/* { dg-do link { target "sh*-*-*" } } */
+/* { dg-do link }  */
 /* { dg-options "-mdiv=call-fp" }  */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 
Index: gcc/testsuite/gcc.target/sh/pr53988.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr53988.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr53988.c	(working copy)
@@ -2,7 +2,7 @@
    values loaded from memory.  If everything goes as expected we won't see
    any sign/zero extensions or and ops.  On SH2A we don't expect to see the
    movu insn.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "tst\tr" 8 } } */
Index: gcc/testsuite/gcc.target/sh/strlen.c
===================================================================
--- gcc/testsuite/gcc.target/sh/strlen.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/strlen.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that the __builtin_strlen function is inlined with cmp/str
    when optimizing for speed.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "jmp" } } */
Index: gcc/testsuite/gcc.target/sh/pr49468-si.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr49468-si.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr49468-si.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that 32 bit integer abs is generated as neg instruction and
    conditional branch instead of default branch-free code.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "neg" 2 } } */
Index: gcc/testsuite/gcc.target/sh/pragma-isr-trap-exit.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pragma-isr-trap-exit.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pragma-isr-trap-exit.c	(working copy)
@@ -1,5 +1,5 @@
 /* Check whether trapa is generated only for an ISR.  */
-/* { dg-do compile { target "sh*-*-*" } }  */
+/* { dg-do compile }  */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
 /* { dg-options "-O" }  */
 /* { dg-final { scan-assembler-times "trapa\[ \t\]\[ \t\]*#4" 1 } }  */
Index: gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-4.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-4.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-4.c	(working copy)
@@ -1,6 +1,6 @@
 /* PR target/50749: Verify that post-increment addressing is generated
    inside a loop.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fmov.s\t@r\[0-9]\+\\+,fr\[0-9]\+" 3 { xfail *-*-*} } } */
Index: gcc/testsuite/gcc.target/sh/pr33135-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr33135-3.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr33135-3.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that fcmp/eq and fcmp/gt instructions are generated when specifying
    -ffinite-math-only and -mieee.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1 -ffinite-math-only -mieee" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fcmp/eq" 4 } } */
Index: gcc/testsuite/gcc.target/sh/pr53512-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr53512-2.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr53512-2.c	(working copy)
@@ -1,6 +1,6 @@
 /* Verify that the fsca insn is not used when specifying -mno-fsca and
   -funsafe-math-optimizations.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1 -mno-fsca -funsafe-math-optimizations" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-not "fsca" } } */
Index: gcc/testsuite/gcc.target/sh/pr54602-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54602-2.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr54602-2.c	(working copy)
@@ -1,7 +1,7 @@
 /* Verify that the delay slot is not stuffed with register pop insns for
    interrupt handler function returns on SH1* and SH2* targets, where the
    rte insn uses the stack pointer.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m1*" "-m2*" } }  */
 /* { dg-final { scan-assembler-times "nop" 1 } } */
Index: gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c	(working copy)
@@ -1,5 +1,5 @@
 /* Verify that we generate movua to load unaligned 32-bit values on SH4A.  */
-/* { dg-do run { target "sh*-*-*" } } */
+/* { dg-do run }  */
 /* { dg-options "-O1 -save-temps -fno-inline" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a*" } }  */
 /* { dg-final { scan-assembler-times "movua.l" 6 } } */
Index: gcc/testsuite/gcc.target/sh/pr52483-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr52483-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr52483-1.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that loads/stores from/to volatile mems don't result in redundant
    sign/zero extensions.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-not "exts|extu" } } */
Index: gcc/testsuite/gcc.target/sh/pr54680.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54680.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr54680.c	(working copy)
@@ -1,7 +1,7 @@
 /* Verify that the fsca input value is not converted to float and then back
    to int.  Notice that we can't count just "lds" insns because mode switches
    use "lds.l".  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2 -mfsca -funsafe-math-optimizations" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m3*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fsca" 7 } } */
Index: gcc/testsuite/gcc.target/sh/pr54760-4.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54760-4.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr54760-4.c	(working copy)
@@ -1,7 +1,7 @@
 /* Check that the GBR address optimization does not combine a gbr store
    and its use when a function call is in between, when GBR is a call used
    register, i.e. it is invalidated by function calls.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1 -fcall-used-gbr" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler "stc\tgbr" } } */
Index: gcc/testsuite/gcc.target/sh/pr52483-5.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr52483-5.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr52483-5.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that loads from volatile mems utilize post-increment addressing
    modes and do not result in redundant sign extensions. */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "@r\[0-9\]\+\\+," 3 } } */
Index: gcc/testsuite/gcc.target/sh/pr54089-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54089-2.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr54089-2.c	(working copy)
@@ -9,7 +9,7 @@
 	mov	r4,r0
 	rts
 	rotcr	r0  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "*"} { "-m3* -m2a* -m4*" } }  */
 /* { dg-final { scan-assembler-not "neg" } } */
Index: gcc/testsuite/gcc.target/sh/pr54386.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54386.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr54386.c	(working copy)
@@ -1,5 +1,5 @@
 /* Check that the inlined mem load is not handled as unaligned load.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-not "shll|extu|or" } } */
Index: gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that the SH specific sh_treg_combine RTL optimization pass works as
    expected.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
 /* { dg-final { scan-assembler-times "tst" 5 } } */
Index: gcc/testsuite/gcc.target/sh/pr56547-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr56547-2.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr56547-2.c	(working copy)
@@ -1,6 +1,6 @@
 /* Verify that the fmac insn is used for the expression 'a * b + a' and
    'a * a + a' when -ffast-math is specified.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1 -ffast-math" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fmac" 2 } } */
Index: gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-4.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-4.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-4.c	(working copy)
@@ -1,6 +1,6 @@
 /* PR target/50749: Verify that post-increment addressing is generated
    inside a loop.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-final { scan-assembler-times "mov.b\t@r\[0-9]\+\\+,r\[0-9]\+" 3 { xfail *-*-*} } } */
 /* { dg-final { scan-assembler-times "mov.w\t@r\[0-9]\+\\+,r\[0-9]\+" 3 { xfail *-*-*} } } */
Index: gcc/testsuite/gcc.target/sh/pr54089-6.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54089-6.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr54089-6.c	(working copy)
@@ -1,5 +1,5 @@
 /* Check that the rotr and rotl instructions are generated.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "rotr" 2 } } */
Index: gcc/testsuite/gcc.target/sh/pr51244-11.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-11.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr51244-11.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that zero-displacement branches are used instead of branch-free
    execution patterns.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1 -mzdcbranch" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "subc|and" } } */
Index: gcc/testsuite/gcc.target/sh/pr50749-sf-predec-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-sf-predec-3.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50749-sf-predec-3.c	(working copy)
@@ -1,6 +1,6 @@
 /* PR target/50749: Verify that pre-decrement addressing is generated
    inside a loop.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fmov.s\tfr\[0-9]\+,@-r\[0-9]\+" 1 } } */
Index: gcc/testsuite/gcc.target/sh/attr-isr-trap_exit.c
===================================================================
--- gcc/testsuite/gcc.target/sh/attr-isr-trap_exit.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/attr-isr-trap_exit.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that trapa / interrput_handler attributes can paired in
    either order.  */
-/* { dg-do compile { target "sh*-*-*" } }  */
+/* { dg-do compile }  */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
 /* { dg-options "-O" }  */
 /* { dg-final { scan-assembler "trapa\[ \t\]\[ \t\]*#4"} }  */
Index: gcc/testsuite/gcc.target/sh/pr51244-15.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-15.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr51244-15.c	(working copy)
@@ -1,7 +1,7 @@
 /* Check that the redundant test removal code in the *cbranch_t split works
    as expected on non-SH2A targets.  Because on SH2A the movrt instruction
    is used, this test is re-used and checked differently in pr51244-16.c.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */
 /* { dg-final { scan-assembler-times "tst" 6 } } */
Index: gcc/testsuite/gcc.target/sh/fpul-usage-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/fpul-usage-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/fpul-usage-1.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that the FPUL register is used when reading a float as an int and
    vice versa, as opposed to pushing and popping the values over the stack.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler "fpul" } } */
Index: gcc/testsuite/gcc.target/sh/pr51244-19.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-19.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr51244-19.c	(working copy)
@@ -23,7 +23,7 @@
    working as expected.  This test requires -O2 because the T bit stores
    in question will be eliminated in additional insn split passes after
    reload.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "movt" } } */
Index: gcc/testsuite/gcc.target/sh/sh2a-bor.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-bor.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/sh2a-bor.c	(working copy)
@@ -1,6 +1,6 @@
 /* Testcase to check generation of a SH2A specific instruction for
    "BOR.B #imm3, @(disp12, Rn)".  */
-/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-do assemble }  */
 /* { dg-options "-O1 -mbitops" } */
 /* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "bor.b"} }  */
Index: gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-2.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-2.c	(working copy)
@@ -1,6 +1,6 @@
 /* PR target/50749: Verify that subsequent pre-decrement addressings
    are generated.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-final { scan-assembler-times "mov.b\tr\[0-9]\+,@-r\[0-9]\+" 5 { xfail *-*-*} } } */
 /* { dg-final { scan-assembler-times "mov.w\tr\[0-9]\+,@-r\[0-9]\+" 5 { xfail *-*-*} } } */
Index: gcc/testsuite/gcc.target/sh/pr55303-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr55303-2.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr55303-2.c	(working copy)
@@ -1,7 +1,7 @@
 /* Verify that for SH2A smax/smin -> cbranch conversion is done properly
    if the clips insn is not used and the expected comparison insns are
    generated.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
 /* { dg-final { scan-assembler-times "cmp/pl" 4 } } */
Index: gcc/testsuite/gcc.target/sh/sp-switch.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sp-switch.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/sp-switch.c	(working copy)
@@ -1,4 +1,4 @@
-/* { dg-do compile { target "sh-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-final { scan-assembler "mov\tr0,r15" } } */
 /* { dg-final { scan-assembler ".long\t_alt_stack" } } */
 
Index: gcc/testsuite/gcc.target/sh/pr51244-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-3.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr51244-3.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that when taking the complement of the T bit on SH2A, 
    the movrt instruction is being generated.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1 -mbranch-cost=2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
 /* { dg-final { scan-assembler-times "movrt" 4 } } */
Index: gcc/testsuite/gcc.target/sh/pr50751-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50751-3.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50751-3.c	(working copy)
@@ -1,7 +1,7 @@
 /* Check that on SH2A the 4 byte mov.b displacement insn is generated to
    handle larger displacements.  If it is generated correctly, there should
    be no base address adjustments outside the mov.b insns.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
 /* { dg-final { scan-assembler-not "add|sub" } } */
Index: gcc/testsuite/gcc.target/sh/pr51244-7.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-7.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr51244-7.c	(working copy)
@@ -10,7 +10,7 @@
 	bra	.L197
 	nop
 */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "cmp/hi" } } */
Index: gcc/testsuite/gcc.target/sh/pr55146.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr55146.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr55146.c	(working copy)
@@ -1,5 +1,5 @@
 /* Check that the 'extu.b' instruction is generated for short jump tables.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-Os" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler "extu.b" } } */
Index: gcc/testsuite/gcc.target/sh/pr50751-7.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50751-7.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50751-7.c	(working copy)
@@ -1,7 +1,7 @@
 /* Check that mov.b and mov.w displacement insns are generated.
    If this is working properly, there should be no base address adjustments
    outside the mov insns.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
 /* { dg-final { scan-assembler-not "add|sub" } } */
Index: gcc/testsuite/gcc.target/sh/pr49880-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr49880-3.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr49880-3.c	(working copy)
@@ -1,5 +1,5 @@
 /* Check that the option -mdiv=call-table works.  */
-/* { dg-do link { target "sh*-*-*" } } */
+/* { dg-do link }  */
 /* { dg-options "-mdiv=call-table" }  */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 
Index: gcc/testsuite/gcc.target/sh/pr51244-20.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-20.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr51244-20.c	(working copy)
@@ -1,7 +1,7 @@
 /* Check that the SH specific sh_treg_combine RTL optimization pass works as
    expected.  On SH2A the expected insns are slightly different, see
    pr51244-21.c.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */
 /* { dg-final { scan-assembler-times "tst" 6 } } */
Index: gcc/testsuite/gcc.target/sh/sh2a-bxor.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-bxor.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/sh2a-bxor.c	(working copy)
@@ -1,6 +1,6 @@
 /* Testcase to check generation of a SH2A specific instruction for
    "BXOR.B #imm3, @(disp12, Rn)".  */
-/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-do assemble }  */
 /* { dg-options "-O1 -mbitops" }  */
 /* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "bxor.b"} }  */
Index: gcc/testsuite/gcc.target/sh/sh4a-fsrra.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh4a-fsrra.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/sh4a-fsrra.c	(working copy)
@@ -1,6 +1,6 @@
 /* Verify that we generate single-precision square root reciprocal
    approximate (fsrra) in fast math mode on SH4A with FPU.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O -ffast-math" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } }  */
 /* { dg-final { scan-assembler "fsrra" } } */
Index: gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-1.c	(working copy)
@@ -1,5 +1,5 @@
 /* PR target/50749: Verify that post-increment addressing is generated.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fmov.s\t@r\[0-9]\+\\+,fr\[0-9]\+" 1 } } */
Index: gcc/testsuite/gcc.target/sh/pr53511-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr53511-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr53511-1.c	(working copy)
@@ -1,5 +1,5 @@
 /* Verify that the fmac insn is used for the standard fmaf function.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler "fmac" } } */
Index: gcc/testsuite/gcc.target/sh/pr21255-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr21255-3.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr21255-3.c	(working copy)
@@ -1,4 +1,4 @@
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2 -fomit-frame-pointer" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m2e" "-m3e" "*single-only" } { "" } }  */
 /* { dg-final { scan-assembler "mov #?0,r.*; mov #?20,r" } } */
Index: gcc/testsuite/gcc.target/sh/pr53512-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr53512-3.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr53512-3.c	(working copy)
@@ -1,6 +1,6 @@
 /* Verify that the fsrra insn is used when specifying -mfsrra and
   -funsafe-math-optimizations and -ffinite-math-only.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1 -mfsrra -funsafe-math-optimizations -ffinite-math-only" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m3*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler "fsrra" } } */
Index: gcc/testsuite/gcc.target/sh/pr33135-4.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr33135-4.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr33135-4.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that only the fcmp/gt instruction is generated when specifying
    -fno-finite-math-only and -mno-ieee.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1 -fno-finite-math-only -mno-ieee" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-not "fcmp/eq" } } */
Index: gcc/testsuite/gcc.target/sh/pr54602-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54602-3.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr54602-3.c	(working copy)
@@ -1,6 +1,6 @@
 /* Verify that the rte delay slot is not stuffed with register pop insns
    which touch the banked registers r0..r7 on SH3* and SH4* targets.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m3*" "-m4*" } }  */
 /* { dg-final { scan-assembler-times "nop" 1 } } */
Index: gcc/testsuite/gcc.target/sh/torture/pr58475.c
===================================================================
--- gcc/testsuite/gcc.target/sh/torture/pr58475.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/torture/pr58475.c	(working copy)
@@ -1,4 +1,4 @@
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 
 int
 kerninfo(int __bsx, double tscale)
Index: gcc/testsuite/gcc.target/sh/torture/pragma-isr.c
===================================================================
--- gcc/testsuite/gcc.target/sh/torture/pragma-isr.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/torture/pragma-isr.c	(working copy)
@@ -1,5 +1,5 @@
 /* Check whether rte is generated for two ISRs.  */
-/* { dg-do compile { target "sh*-*-*" } }  */
+/* { dg-do compile }  */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "rte" 2 } }  */
 
Index: gcc/testsuite/gcc.target/sh/torture/pragma-isr2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/torture/pragma-isr2.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/torture/pragma-isr2.c	(working copy)
@@ -1,5 +1,5 @@
 /* Check whether rte is generated only for an ISRs.  */
-/* { dg-do compile { target "sh*-*-*" } }  */
+/* { dg-do compile }  */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "rte" 1 } }  */
 
Index: gcc/testsuite/gcc.target/sh/torture/pr58314.c
===================================================================
--- gcc/testsuite/gcc.target/sh/torture/pr58314.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/torture/pr58314.c	(working copy)
@@ -1,4 +1,4 @@
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-Os" } */
 
 typedef unsigned short __u16;
Index: gcc/testsuite/gcc.target/sh/torture/pr34777.c
===================================================================
--- gcc/testsuite/gcc.target/sh/torture/pr34777.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/torture/pr34777.c	(working copy)
@@ -1,4 +1,4 @@
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-additional-options "-fschedule-insns -fPIC -mprefergot" }  */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
 
Index: gcc/testsuite/gcc.target/sh/pr54760-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54760-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr54760-1.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that the __builtin_thread_pointer and __builtin_set_thread_pointer
    built-in functions result in gbr store / load instructions.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "ldc" 1 } } */
Index: gcc/testsuite/gcc.target/sh/pr52483-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr52483-2.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr52483-2.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that loads/stores from/to volatile mems utilize displacement
    addressing modes and do not result in redundant sign/zero extensions. */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "@\\(5," 4 } } */
Index: gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-1.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-1.c	(working copy)
@@ -1,5 +1,5 @@
 /* PR target/50749: Verify that post-increment addressing is generated.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-final { scan-assembler-times "mov.b\t@r\[0-9]\+\\+,r\[0-9]\+" 1 } } */
 /* { dg-final { scan-assembler-times "mov.w\t@r\[0-9]\+\\+,r\[0-9]\+" 1 } } */
Index: gcc/testsuite/gcc.target/sh/pr49468-di.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr49468-di.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr49468-di.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that 64 bit integer abs is generated as negc instruction pairs
    and conditional branch instead of default branch-free code.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "negc" 4 } } */
Index: gcc/testsuite/gcc.target/sh/pr54089-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54089-3.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr54089-3.c	(working copy)
@@ -1,7 +1,7 @@
 /* The dynamic shift library functions truncate the shift count to 5 bits.
    Verify that this is taken into account and no extra shift count
    truncations are generated before the library call.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m1*" "-m2" "-m2e*" } } */
 /* { dg-final { scan-assembler-not "and" } } */
Index: gcc/testsuite/gcc.target/sh/pr54685.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54685.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr54685.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that a comparison 'unsigned int <= 0x7FFFFFFF' results in code
    utilizing the cmp/pz instruction.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-not "not\[ \t\]" } } */
Index: gcc/testsuite/gcc.target/sh/pr54089-7.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54089-7.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr54089-7.c	(working copy)
@@ -1,5 +1,5 @@
 /* Check that the rotcr instruction is generated.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "rotcr" 4 } } */
Index: gcc/testsuite/gcc.target/sh/pr50749-sf-predec-4.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-sf-predec-4.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr50749-sf-predec-4.c	(working copy)
@@ -1,6 +1,6 @@
 /* PR target/50749: Verify that pre-decrement addressing is generated
    inside a loop.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fmov.s\tfr\[0-9]\+,@-r\[0-9]\+" 3 { xfail *-*-*} } } */
Index: gcc/testsuite/gcc.target/sh/sh4a-sincosf.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh4a-sincosf.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/sh4a-sincosf.c	(working copy)
@@ -1,7 +1,7 @@
 /* Verify that we generate a single single-precision sine and cosine
    approximate (fsca) in fast math mode when a function computes both
    sine and cosine.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O -ffast-math" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } }  */
 /* { dg-final { scan-assembler-times "fsca" 1 } } */
Index: gcc/testsuite/gcc.target/sh/pr51244-12.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-12.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr51244-12.c	(working copy)
@@ -1,7 +1,7 @@
 /* Check that the negc instruction is generated as expected for the cases
    below.  If we see a movrt or #-1 negc sequence it means that the pattern
    which handles the inverted case does not work properly.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-times "negc" 10 } } */
Index: gcc/testsuite/gcc.target/sh/rte-delay-slot.c
===================================================================
--- gcc/testsuite/gcc.target/sh/rte-delay-slot.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/rte-delay-slot.c	(working copy)
@@ -1,4 +1,4 @@
-/* { dg-do compile { target "sh-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } "*" "-m1 -m2*" }  */
 /* { dg-final { scan-assembler-not "\trte\t\n\tmov.l\t@r15\\+" } } */
Index: gcc/testsuite/gcc.target/sh/pr51244-16.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-16.c	(revision 204476)
+++ gcc/testsuite/gcc.target/sh/pr51244-16.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that the redundant test removal code in the *cbranch_t split works
    as expected on SH2A targets.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile }  */
 /* { dg-options "-O2" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
 /* { dg-final { scan-assembler-times "tst" 6 } } */

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