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Re: [PATCH] LRA: Fix incorrect register spill/reload

On 11/1/2013, 3:45 PM, Jeff Law wrote:
On 10/31/13 14:03, Robert Suchanek wrote:
Hi David,

No, I do not have read/write SVN access. I know a person who could commit the patch for me, however, if you can commit it, I'd be grateful.
Note, I didn't see anywhere in this thread an indication this test had been through a bootstrap and regression testing. I was running those overnight on Robert's behalf and the bootstrap test failed with a comparison failure between stage2/toplev.o and stage3/toplev.o

Vlad, when approving patches, please make sure they've been through the usual bootstrap and regression testing procedures. If the contributor hasn't done it themselves, you can either do it for them or ask them to do it.

I trust y'all will address the problem appropriately.

I've tried many bootstraps on the current trunk with this patch (x86_64, i686, x86_64 with arch corei7, with tune corei7). I have no problems.

I did not expected from the patch any problems too. It is so obvious. This simple change should not affect x86 (or any other target currently using LRA). The code in question is used only for x86-64 and only for modern intel processing tuning. It is about accuracy of using SSE regs (regs_ever_live) which as I know affects only on saving/restoring regs in prologue/epilogue. As all SSE_REGS are only call-clobbered, the accuracy of this info does not affect code generation.

I suspect, the reason for your bootstrap failure was in another patch or you use bootstrap specific options.


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