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Re: [PATCH, i386, MPX, 1/X] Support of Intel MPX ISA. 1/2 Bound type and modes
- From: Richard Henderson <rth at redhat dot com>
- To: Jeff Law <law at redhat dot com>, Ilya Enkovich <enkovich dot gnu at gmail dot com>, gcc-patches <gcc-patches at gcc dot gnu dot org>
- Date: Tue, 22 Oct 2013 12:31:28 -0700
- Subject: Re: [PATCH, i386, MPX, 1/X] Support of Intel MPX ISA. 1/2 Bound type and modes
- Authentication-results: sourceware.org; auth=none
- References: <20130917081856 dot GB60115 at msticlxl57 dot ims dot intel dot com> <CAMbmDYYcdYrcAJEWeQ=2YkKMCpkqKzf4JeW=gF2tRuUBKh3gUA at mail dot gmail dot com> <CAMbmDYYz0zzsxRce9kGgzd0ALG=LstY49H4rY9dXHuAJzoYt6A at mail dot gmail dot com> <52656DFC dot 4060807 at redhat dot com> <5266CE14 dot 9010703 at redhat dot com> <5266CF7B dot 1030807 at redhat dot com>
On 10/22/2013 12:18 PM, Jeff Law wrote:
>> The only way I could think to positively ensure that normal operations
>> didn't get implemented via mpx insns is to describe the new patterns
>> with distinct modes.
> Presumably once we have a distinct mode, we do the right magic in
> HARD_REGNO_MODE_OK and that's how you get your guarantee. I'm assuming we're
> exposing these to the register allocator (I haven't looked at the full series
> yet).
Yeah, the register allocator was supposed to be involved.
(And I need to review the series myself.)
> Presumably you need a distinct mode coming out of the front-end/gimple to
> ensure we get the new mode in RTL.
Yes, which is where I believe the new types come from as well.
r~
- References:
- Re: [PATCH, i386, MPX, 1/X] Support of Intel MPX ISA. 1/2 Bound type and modes
- Re: [PATCH, i386, MPX, 1/X] Support of Intel MPX ISA. 1/2 Bound type and modes
- Re: [PATCH, i386, MPX, 1/X] Support of Intel MPX ISA. 1/2 Bound type and modes
- Re: [PATCH, i386, MPX, 1/X] Support of Intel MPX ISA. 1/2 Bound type and modes
- Re: [PATCH, i386, MPX, 1/X] Support of Intel MPX ISA. 1/2 Bound type and modes