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Re: [PATCH i386 AVX2] Remove redundant expands.
- From: Uros Bizjak <ubizjak at gmail dot com>
- To: Richard Henderson <rth at redhat dot com>
- Cc: Kirill Yukhin <kirill dot yukhin at gmail dot com>, GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Wed, 16 Oct 2013 20:42:10 +0200
- Subject: Re: [PATCH i386 AVX2] Remove redundant expands.
- Authentication-results: sourceware.org; auth=none
- References: <20131016160621 dot GB22220 at msticlxl57 dot ims dot intel dot com> <CAFULd4YvP_CJbKf+CFky20pQMjDUXbc0GESZZBqSpc3TvXckHA at mail dot gmail dot com> <525EC654 dot 1000808 at redhat dot com>
On Wed, Oct 16, 2013 at 7:01 PM, Richard Henderson <firstname.lastname@example.org> wrote:
> On 10/16/2013 09:47 AM, Uros Bizjak wrote:
>> On Wed, Oct 16, 2013 at 6:06 PM, Kirill Yukhin <email@example.com> wrote:
>>> It seems that gang of AVX* patterns were copy and
>>> pasted from SSE, however as far as they are NDD,
>>> we may remove corresponding expands which sort operands.
>> OTOH, I have some second thoughts on removing AVX2 expanders.
>> Please consider the situation, where we have *both* operands in
>> memory, and the insn is inside the loop. When reload comes around, it
>> will fixup one of the operands with a load from memory. However,
>> having insn in the loop, I suspect the load won't be moved out of
>> So, I guess even AVX/AVX2 insn patterns should call
>> ix86_fixup_binary_operands_*, and this fixup function should be
>> improved to load one of the operands into register, in case both
>> operands are in memory.
>> This also means, that you still need expanders for AVX512 commutative
> Fair enough.
I have checked ix86_fixup_binary_operands and ix86_binary_operator_ok,
and they should be OK for destructive (SSE2) and non-destructive (AVX)
commutative instructions. Vector instructions have always destination
in a register, so most of fixups and checks do not apply at all. We
can probably use:
if (MEM_P (operands) && MEM_P (operands))
operands = force_reg (<MODE>mode, operands);
in expanders and
!(MEM_P (operands) && MEM_P (operands))
in insn constraints for most of SSE and AVX commutative insns.