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Re: [ARM/AARCH64] Remodel type attribute values for Neon Instructions.
- From: Richard Earnshaw <rearnsha at arm dot com>
- To: James Greenhalgh <James dot Greenhalgh at arm dot com>
- Cc: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>, Marcus Shawcroft <Marcus dot Shawcroft at arm dot com>, Ramana Radhakrishnan <Ramana dot Radhakrishnan at arm dot com>
- Date: Tue, 15 Oct 2013 15:21:03 +0100
- Subject: Re: [ARM/AARCH64] Remodel type attribute values for Neon Instructions.
- Authentication-results: sourceware.org; auth=none
- References: <1381836226-430-1-git-send-email-james dot greenhalgh at arm dot com>
On 15/10/13 12:23, James Greenhalgh wrote:
> The historical neon_type attribute formed groups over the Neon
> instructions which were well suited for modelling the Cortex-A8
> pipeline, but were cumbersome for other processor models.
> The AArch64 has another classification "simd_type". This is, with a
> few exceptions, and when augmented by simd_mode, suitably high
> resolution for our needs. However, this is not integrated in to the
> "type" attribute, which we would ideally like to be the One True
> instruction classification attribute.
> This patch series aims to solve these problems by defining a new,
> high resolution classification across the Neon instructions. From
> this we can derive two benefits:
> * Convergence between the A32 and A64 backends.
> * Better Pipeline modeling.
> The patch series first introduces the new Neon type classifications,
> then updates config/arm/neon.md and config/aarch64/aarch64-simd.md
> to use the new classifications.
> We then update the pipeline models for the new types. For Cortex-A8
> and Cortex-A9, this simply means reforming the old groups. For Cortex-A15,
> this is a chance to form new groups with which we can better model the
> pipeline latencies.
> Finally, we can remove the old types and config/arm/neon-schedgen.ml.
> The patch series has been bootstrapped on a Chromebook and the full
> testsuite run with no regressions. All pipeline models have been
> checked against some sample neon intrinsics code to ensure the new
> schedules are sensible, and there are no holes in the pipeline models.
> James Greenhalgh (10):
> [ARM] [1/10] Add new types to describe Neon insns.
> [AArch64] [Neon types 2/10] Update Current type attributes to new Neon
> [ARM] [Neon types 3/10] Update Current type attributes to new Neon
> [AArch64] [Neon types 4/10] Add type attributes to all simd insns
> [ARM] [Neon types 5/10] Update Cortex-A8 pipeline model
> [ARM] [Neon types 6/10] Cortex-A9 neon pipeline changes
> [ARM] [Neon types 7/10] Cortex-A15 neon pipeline changes
> [ARM] [Neon types 8/10] Cortex-A7 neon pipeline model
> [ARM] [Neon types 9/10] Remove old neon types
> [ARM] [Neon types 10/10] Remove neon-schedgen.ml
All of the above are OK.