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Re: [PATCH] Workaround errata for the PMC-Sierra RM7000 cpu.


On Thu, 10 Oct 2013, Richard Sandiford wrote:

> Ideally opcodes/mips*.c would have a flag to mark load instructions,
> but all we have at the moment are flags to mark load delays, which means
> that LD and some other load instructions don't have them.  So I can think
> of three options:
> 
> (1) Turn INSN_LOAD_MEMORY_DELAY into INSN_LOAD_GPR and
>     INSN_COPRO_MEMORY_DELAY into INSN_LOAD_COPRO.  Add the flags to all
>     loads in the opcode table that don't currently have one.
> 
>     This would be the best approach, but I can understand why it might
>     seem like too much effort.

 I second this suggestion, except that I'd leave INSN_COPRO_MEMORY_DELAY 
alone at this time.  Otherwise we'd be hitting the grey area of the MT 
ASE's MFTR instruction for no real use (yes, you can use it to read self).  
I think the big issue here will be identifying all the exotic memory load 
instructions vendors may have invented (anything starting with `L' is an 
obvious candidate, but there are other cases too, e.g. all the SWAP* 
stuff; the presence of `b' among the operand specifiers can help, however 
is not a guarantee either way), but otherwise it's a pure mechanical `sed' 
(or equivalent) application.

  Maciej


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