[PATCH] reimplement -fstrict-volatile-bitfields v4, part 2/2

[Sandra Loosemore <sandra at codesourcery dot com>]

This patch makes -fstrict-volatile-bitfields not be the default on any 
target.  It is unchanged from part 4 of the previous version (v3) of 
this patch set that I originally posted back in June and have been 
re-pinging many times since then.

Some reviewers of my original patch series argued quite strongly that 
the C/C++ language semantics ought to take precedence over any 
target-specific ABI in cases where they conflict.  I am neutral on this 
change myself, but if it is a requirement for approval of the other part 
of the patch that fixes the wrong-code bugs, I think users on targets 
such as ARM that currently default to enabling this flag would be better 
off specifying the flag explicitly to get code that does what they want, 
than getting broken code by default and no way to tell GCC to DTRT.  :-( 
 And that's the behavior we're stuck with if we do nothing or can't 
reach a consensus about what to do.  :-(

Bernd Edlinger has been working on a followup patch to issue warnings in 
cases where -fstrict-volatile-bitfields behavior conflicts with the new 
C/C++ memory model, which might help to ease the transition in the 
change of defaults.  I believe this was the last version posted:

http://gcc.gnu.org/ml/gcc-patches/2013-09/msg00100.html

-Sandra

2013-09-28  Sandra Loosemore  <sandra@codesourcery.com>

	gcc/
	* config/aarch64/aarch64.c (aarch64_override_options): Don't
	override flag_strict_volatile_bitfields.
	* config/arm/arm.c (arm_option_override): Likewise.
	* config/h8300/h8300.c (h8300_option_override): Likewise.
	* config/m32c/m32c.c (m32c_option_override): Likewise.
	* config/rx/rx.c (rx_option_override): Likewise.
	* config/sh/sh.c (sh_option_override): Likewise.
	* doc/invoke.texi (Code Gen Options): Document that
	-fstrict-volatile-bitfields is no longer the default on any target.

	gcc/testsuite/
	* gcc.target/arm/volatile-bitfields-1.c: Add explicit
	-fstrict-volatile-bitfields.
	* gcc.target/arm/volatile-bitfields-2.c: Likewise.
	* gcc.target/arm/volatile-bitfields-3.c: Likewise.
	* gcc.target/arm/volatile-bitfields-4.c: Likewise.

Index: gcc/config/aarch64/aarch64.c
===================================================================
--- gcc/config/aarch64/aarch64.c	(revision 203002)
+++ gcc/config/aarch64/aarch64.c	(working copy)
@@ -5141,10 +5141,6 @@ aarch64_override_options (void)
 
   aarch64_build_bitmask_table ();
 
-  /* This target defaults to strict volatile bitfields.  */
-  if (flag_strict_volatile_bitfields < 0 && abi_version_at_least (2))
-    flag_strict_volatile_bitfields = 1;
-
   /* If the user did not specify a processor, choose the default
      one for them.  This will be the CPU set during configuration using
      --with-cpu, otherwise it is "generic".  */
Index: gcc/config/arm/arm.c
===================================================================
--- gcc/config/arm/arm.c	(revision 203002)
+++ gcc/config/arm/arm.c	(working copy)
@@ -2136,11 +2136,6 @@ arm_option_override (void)
 			   global_options.x_param_values,
 			   global_options_set.x_param_values);
 
-  /* ARM EABI defaults to strict volatile bitfields.  */
-  if (TARGET_AAPCS_BASED && flag_strict_volatile_bitfields < 0
-      && abi_version_at_least(2))
-    flag_strict_volatile_bitfields = 1;
-
   /* Enable sw prefetching at -O3 for CPUS that have prefetch, and we have deemed
      it beneficial (signified by setting num_prefetch_slots to 1 or more.)  */
   if (flag_prefetch_loop_arrays < 0
Index: gcc/config/h8300/h8300.c
===================================================================
--- gcc/config/h8300/h8300.c	(revision 203002)
+++ gcc/config/h8300/h8300.c	(working copy)
@@ -437,10 +437,6 @@ h8300_option_override (void)
 	 restore er6 though, so bump up the cost.  */
       h8300_move_ratio = 6;
     }
-
-  /* This target defaults to strict volatile bitfields.  */
-  if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
-    flag_strict_volatile_bitfields = 1;
 }
 
 /* Return the byte register name for a register rtx X.  B should be 0
Index: gcc/config/m32c/m32c.c
===================================================================
--- gcc/config/m32c/m32c.c	(revision 203002)
+++ gcc/config/m32c/m32c.c	(working copy)
@@ -416,10 +416,6 @@ m32c_option_override (void)
   if (TARGET_A24)
     flag_ivopts = 0;
 
-  /* This target defaults to strict volatile bitfields.  */
-  if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
-    flag_strict_volatile_bitfields = 1;
-
   /* r8c/m16c have no 16-bit indirect call, so thunks are involved.
      This is always worse than an absolute call.  */
   if (TARGET_A16)
Index: gcc/config/rx/rx.c
===================================================================
--- gcc/config/rx/rx.c	(revision 203002)
+++ gcc/config/rx/rx.c	(working copy)
@@ -2691,10 +2691,6 @@ rx_option_override (void)
 	  }
       }
 
-  /* This target defaults to strict volatile bitfields.  */
-  if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
-    flag_strict_volatile_bitfields = 1;
-
   rx_override_options_after_change ();
 
   if (align_jumps == 0 && ! optimize_size)
Index: gcc/config/sh/sh.c
===================================================================
--- gcc/config/sh/sh.c	(revision 203002)
+++ gcc/config/sh/sh.c	(working copy)
@@ -1014,10 +1014,6 @@ sh_option_override (void)
   if (sh_fixed_range_str)
     sh_fix_range (sh_fixed_range_str);
 
-  /* This target defaults to strict volatile bitfields.  */
-  if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
-    flag_strict_volatile_bitfields = 1;
-
   /* Parse atomic model option and make sure it is valid for the current
      target CPU.  */
   selected_atomic_model_
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi	(revision 203003)
+++ gcc/doc/invoke.texi	(working copy)
@@ -21175,8 +21175,11 @@
 case GCC falls back to generating multiple accesses rather than code that 
 will fault or truncate the result at run time.
 
-The default value of this option is determined by the application binary
-interface for the target processor.
+Note that in some cases this option overrides the memory model
+specified in recent versions of the C and C++ standards.  For this
+reason, @option{-fstrict-volatile-bitfields} is not enabled by default
+on any target, even those where the application binary interface for
+the target processor requires this behavior.
 
 @item -fsync-libcalls
 @opindex fsync-libcalls
Index: gcc/testsuite/gcc.target/arm/volatile-bitfields-1.c
===================================================================
--- gcc/testsuite/gcc.target/arm/volatile-bitfields-1.c	(revision 203002)
+++ gcc/testsuite/gcc.target/arm/volatile-bitfields-1.c	(working copy)
@@ -1,6 +1,6 @@
 /* { dg-require-effective-target arm_eabi } */
 /* { dg-do compile } */
-/* { dg-options "-O2" } */
+/* { dg-options "-O2 -fstrict-volatile-bitfields" } */
 
 typedef struct {
   char a:1;
Index: gcc/testsuite/gcc.target/arm/volatile-bitfields-2.c
===================================================================
--- gcc/testsuite/gcc.target/arm/volatile-bitfields-2.c	(revision 203002)
+++ gcc/testsuite/gcc.target/arm/volatile-bitfields-2.c	(working copy)
@@ -1,6 +1,6 @@
 /* { dg-require-effective-target arm_eabi } */
 /* { dg-do compile } */
-/* { dg-options "-O2" } */
+/* { dg-options "-O2 -fstrict-volatile-bitfields" } */
 
 typedef struct {
   volatile unsigned long a:8;
Index: gcc/testsuite/gcc.target/arm/volatile-bitfields-3.c
===================================================================
--- gcc/testsuite/gcc.target/arm/volatile-bitfields-3.c	(revision 203002)
+++ gcc/testsuite/gcc.target/arm/volatile-bitfields-3.c	(working copy)
@@ -1,6 +1,6 @@
 /* { dg-require-effective-target arm_eabi } */
 /* { dg-do compile } */
-/* { dg-options "-O2" } */
+/* { dg-options "-O2 -fstrict-volatile-bitfields" } */
 
 typedef struct {
   volatile unsigned long a:8;
Index: gcc/testsuite/gcc.target/arm/volatile-bitfields-4.c
===================================================================
--- gcc/testsuite/gcc.target/arm/volatile-bitfields-4.c	(revision 203002)
+++ gcc/testsuite/gcc.target/arm/volatile-bitfields-4.c	(working copy)
@@ -1,6 +1,6 @@
 /* { dg-require-effective-target arm_eabi } */
 /* { dg-do compile } */
-/* { dg-options "-O2" } */
+/* { dg-options "-O2 -fstrict-volatile-bitfields" } */
 /* { dg-final { scan-assembler-times "ldr\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" 2 } } */
 /* { dg-final { scan-assembler-times "str\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" 2 } } */
 /* { dg-final { scan-assembler-not "strb" } } */