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Re: [PATCH, powerpc] Rework#2 VSX scalar floating point support, patch #3

On Thu, Sep 26, 2013 at 06:56:37PM -0400, David Edelsohn wrote:
> On Thu, Sep 26, 2013 at 4:51 PM, Michael Meissner
> <> wrote:
> > I discovered that I was setting the wv/wu constraints incorrectly to
> > ALTIVEC_REGS, which leads to reload failures in some cases.
> >
> > Is this patch ok to apply along with the previous patch assuming it bootstraps
> > and has no regressions with make check?  It builds the programs that had
> > failures with the previous patch.
> >
> > 2013-09-26  Michael Meissner  <>
> >
> >         * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Don't
> >         allow wv/wu constraints to be ALTIVEC_REGISTERS unless DF/SF can
> >         occupy the Altivec registers.
> Okay.
> Can you add a testcase to catch this in the future?

You only see it in big programs with agressive optimizations.  I did not see it
during the normal testing (bootstrap, etc.).

The failure is reload complaining it can't find an Altivec register to spill if
the move pattern has an option for only Altivec registers.  It isn't like bad
code is silently generated.  I will check the 5 spec benchmarks that failed
with to see if I can extract one module that shows it off.

Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460, USA
email:, phone: +1 (978) 899-4797

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