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[AArch64] Fix categorisation of the frecp* insns.


Hi,

It looks like the frecp instructions got miscategorised as TARGET_FLOAT
instructions when they are in fact TARGET_SIMD instructions.

Move them to the right file, give them a simd_type, drop their "type"
and "v8type" and clean up the useless types from aarch64.md.

Also, where possible merge patterns.

Tested on aarch64-none-elf with no regression.

Thanks,
James

---
2013-09-03  James Greenhalgh   <james.greenhalgh@arm.com>

	* config/aarch64/aarch64.md
	(type): Remove frecpe, frecps, frecpx.
	(aarch64_frecp<FRECP:frecp_suffix><mode>): Move to aarch64-simd.md,
	fix to be a TARGET_SIMD instruction.
	(aarch64_frecps): Remove.
	* config/aarch64/aarch64-simd.md
	(aarch64_frecp<FRECP:frecp_suffix><mode>): New, moved from aarch64.md
 	(aarch64_frecps<mode>): Handle all float/vector of float modes.
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index f4b929edf44fbeebe6da2568a3aa76138eca0609..c085fb9c49958c5f402a28c0b39fe45ec1aadbc7 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -4179,13 +4179,23 @@ (define_insn "aarch64_frecpe<mode>"
    (set_attr "simd_mode" "<MODE>")]
 )
 
+(define_insn "aarch64_frecp<FRECP:frecp_suffix><mode>"
+  [(set (match_operand:GPF 0 "register_operand" "=w")
+	(unspec:GPF [(match_operand:GPF 1 "register_operand" "w")]
+		    FRECP))]
+  "TARGET_SIMD"
+  "frecp<FRECP:frecp_suffix>\\t%<s>0, %<s>1"
+  [(set_attr "simd_type" "simd_frecp<FRECP:frecp_suffix>")
+   (set_attr "mode" "<MODE>")]
+)
+
 (define_insn "aarch64_frecps<mode>"
-  [(set (match_operand:VDQF 0 "register_operand" "=w")
-	(unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w")
-		     (match_operand:VDQF 2 "register_operand" "w")]
+  [(set (match_operand:VALLF 0 "register_operand" "=w")
+	(unspec:VALLF [(match_operand:VALLF 1 "register_operand" "w")
+		     (match_operand:VALLF 2 "register_operand" "w")]
 		    UNSPEC_FRECPS))]
   "TARGET_SIMD"
-  "frecps\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+  "frecps\\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
   [(set_attr "simd_type" "simd_frecps")
    (set_attr "simd_mode" "<MODE>")]
 )
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 47532fca2c550e8ec9b63898511ef6c276943a45..a46dd5813acd9c800a6c519544fb7bca5de993d9 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -240,9 +240,6 @@ (define_attr "v8type"
    fmovf2i,\
    fmovi2f,\
    fmul,\
-   frecpe,\
-   frecps,\
-   frecpx,\
    frint,\
    fsqrt,\
    load_acq,\
@@ -3946,29 +3943,6 @@ (define_insn "smin<mode>3"
    (set_attr "mode" "<MODE>")]
 )
 
-(define_insn "aarch64_frecp<FRECP:frecp_suffix><mode>"
-  [(set (match_operand:GPF 0 "register_operand" "=w")
-	(unspec:GPF [(match_operand:GPF 1 "register_operand" "w")]
-		    FRECP))]
-  "TARGET_FLOAT"
-  "frecp<FRECP:frecp_suffix>\\t%<s>0, %<s>1"
-  [(set_attr "v8type" "frecp<FRECP:frecp_suffix>")
-   (set_attr "type" "ffarith<s>")
-   (set_attr "mode" "<MODE>")]
-)
-
-(define_insn "aarch64_frecps<mode>"
-  [(set (match_operand:GPF 0 "register_operand" "=w")
-	(unspec:GPF [(match_operand:GPF 1 "register_operand" "w")
-		     (match_operand:GPF 2 "register_operand" "w")]
-		    UNSPEC_FRECPS))]
-  "TARGET_FLOAT"
-  "frecps\\t%<s>0, %<s>1, %<s>2"
-  [(set_attr "v8type" "frecps")
-   (set_attr "type" "ffarith<s>")
-   (set_attr "mode" "<MODE>")]
-)
-
 ;; -------------------------------------------------------------------
 ;; Reload support
 ;; -------------------------------------------------------------------

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