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Re: [PATCH 1/n] Add conditional compare support
- From: Richard Earnshaw <rearnsha at arm dot com>
- To: Richard Biener <richard dot guenther at gmail dot com>
- Cc: Zhenqiang Chen <Zhenqiang dot Chen at arm dot com>, GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Tue, 27 Aug 2013 12:56:54 +0100
- Subject: Re: [PATCH 1/n] Add conditional compare support
- Authentication-results: sourceware.org; auth=none
- References: <000001ce9e58$6dadf230$4909d690$ at arm dot com> <CAFiYyc25hLxrAnsOXbfqYo=Rsw_MDopxb66bygfac-CEsffOEw at mail dot gmail dot com>
On 27/08/13 12:10, Richard Biener wrote:
> What's this for and what's the desired semantics? I don't like having
> extra tree codes for this. Is this for a specific instruction set
The background is to support the conditional compare instructions in ARM
(more effectively) and AArch64 at all.
The current method used in ARM is to expand into a series of store-flag
instructions and then hope that combine can optimize them away (though
that fails far too often, particularly when the first instruction in the
sequence is combined into another pattern). To make it work at all the
compiler has to lie about the costs of various store-flag type
operations which overall risks producing worse code and means we also
have to support many more complex multi-instruction patterns than is
desirable. I really don't want to go down the same route for AArch64.
The idea behind all this is to capture potential conditional compare
operations early enough in the mid end that we can keep track of them
until RTL expand time and then to emit the correct logic on all targets
depending on what is the best thing for that target. The current method
of lowering into store-flag sequences doesn't really cut it.