This is the mail archive of the
mailing list for the GCC project.
Re: [PATCH] x86-64 gcc generate wrong assembly instruction movabs for intel syntax
- From: Uros Bizjak <ubizjak at gmail dot com>
- To: Perez Read <netfirewall at gmail dot com>
- Cc: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Date: Mon, 12 Aug 2013 11:26:45 +0200
- Subject: Re: [PATCH] x86-64 gcc generate wrong assembly instruction movabs for intel syntax
- References: <CAFULd4YQZKujRexrf77+CK9=Ru-Oq9pJMwtiTJJ+xn-9oZgykg at mail dot gmail dot com> <CAEZeYNW3tEtPfbfhstHGx4=1C0rPH1b---jPACjVbi8EOpyjNQ at mail dot gmail dot com>
On Mon, Aug 12, 2013 at 11:24 AM, Perez Read <email@example.com> wrote:
>>> movabs is incorrectly translated into "mov [rax], -1", and causes
>>> compile error "Error: ambiguous operand size for `mov' ".
>>> It should be "mov QWORD PTR [rax], -1"
>>> Bootstrap passed. Regression tested on x86_64-unknown-linux-gnu (pc).
>>> 2013-08-10 Perez Read <firstname.lastname@example.org>
>>> * config/i386/i386.md (*movabs<mode>_1) : Add <ptrsize> PTR before
>>> operand 0 for intel asm alternative.
>>> * testsuite/gcc.target/i386/movabs-1.c : New test.
>> You should mention PR number in the ChangeLog.
>> Looks OK, but I think that for consistency this decoration should also
>> be added to *movabs<mode>_2 pattern.
> After the test, I think we can skip this pattern.
> Because the operand 0 must be the register, the assembler will
> determine the size automatically.
As said, I don't want two similar patterns with a different asm
template in i386.md. So, if decorating movabs<mode>_2 works OK, I
propose to change both patterns with your change.