Re: cfgexpand.c patch for msp430-elf

[Jeff Law <law at redhat dot com>]

Sorry, I must have missed this as being a partial integer issue.

The partial integer modes have the same size/precision as their normal 
sized cousins in terms of GCC's representation.  However, they also have 
a target dependent implicit precision which is not exposed to GCC.  PSI 
modes have always been implemented this way -- I did a PSImode target 
back in 1997 or so.

It is assumed that the target will provide the necessary patterns and 
support for converting to/from the partial modes.  Those patters are a 
bit opaque as GCC doesn't know the exact width of the PSImode object and 
as such we don't try to optimize this stuff much at all.  Note that a 
target using partial integer modes has to do something sensible with 
TRULY_NOOP_TRUNCATION as well.  The target is also responsible for 
making sure the right things happen with pointer arithmetic.

As a poor bastard who's actually done a port to a target with 24bit wide 
address registers, DJ's patch absolutely makes sense.  I can't comment 
on the FRACTIONAL modes as they didn't exist when I had to do the mn102 
port.

The only concern I would have would be cases where op0 & op1 are both 
using full modes of the same size, but aren't equal.  The most obvious 
would be integer vs floating modes.  However, in this code we're dealing 
strictly with POINTER_PLUS_EXPR and can safely assume we're dealing with 
integer modes.

I'd probably twiddle the code slightly to have another condition like:

  /* If OP0 is a partial mode, then we must truncate, even if it has
     the same bitsize as OP1 as GCC's representation of partial modes
     is opaque.  */
  || (GET_MODE_CLASS (GET_MODE (op0)) == MODE_PARTIAL
      && GET_MODE_BITSIZE (GET_MODE (op0)) == GET_MODE_BITSIZE 
(GET_MODE (op1))

Approved with a change similar to that, assuming it works.

jeff